8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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FLOPPY DISK Fe I tNITTEI/CONTROLLER 81330 BIPOLAR LSI DIVISION 22 21 20 19 18 17 16 15 14 13 12 11 10 ~ TEST POINT VCC \\ ~ ~C1 ~ /25C 1.....m C2 ~~ ~~X1 8X330 /. CJ ~~ C" " ~ 'DW~ • OW OUTPUT PULSE RATE = FCCO/16 'M 5K \ 35 CCO PF ~ I-- OC ~ ~ V LOAD REGISTERS: III UI ::IE BITS - 0 1 2 3 4 5 6 7 70C ".. ~ 1328 - 0 1 1 1 X X X X 1338 - X 1 X X X 1 1 1 1378 - 1 1 1 1 1 1 1 1 ~ ~ ~ ....... ~ ~ ~ --II!!!.... CAPACITANCE IN PICOFARADS .... 1IIIIIIII:= ~ -- ~ Figure 10. Capacitance-versus-Frequency with: VCC = 5V, VCR = 2.5V, and 1= 300J,LA VCC - - - - I-- I-- I-- - - - - VOLTAGE REGULATOR All internal logic of the 8X330 is powered by an on-chip voltage regulator that requires an external series-pass transistor. Electrical specifications for the off-chip power transistor and a typical hook-up are shown in accompanying diagrams. To minimize lead inductance, the transistor should be as close as possible to the 8X330 package and the emitter should be ac-grounded via a 0.1-microfarad capacitor. TYPICAL HOOK-UP ORDERING INFORMATION Order number: N8X330 Packaging information: Refer to Signetics price list Supply voltage: SV (±S%) Operating temperature range: O°C to +70°C VCC 8X330 ELECTRICAL SPECIFICATIONS *PARAMETER CONDITIONS hfe VSEON VCESAT BVCEO ft VeE = 2V VCE = SV/lc = SOOmA Ic = SOO mAils = SO mA LIMITS >SO 30 MHz 'Medium power NPN silicon (Q°
2048 BII BlrOtliliM (25618) PRELIMINARY SPECIFICATION 81350 (I S ) 8X350-F DESCRIPTION The 8X350 bipolar RAM is designed principally as a working storage element in an 8X300 based system. Internal circuitry is provided for direct use in 8X300 applications. When used with the 8X300, the RAM address and data buses are tied together and connected to the IV bus of the system. TYPICAL I/O STRUCTURE +v +v PIN CONFIGURATION F PACKAGE The data inputs and outputs share a common 110 bus with 3-state outputs. The 8X350 is available in commercial and military temperature ranges. For the commercial temperature range (O°C to +75°C) specify N8X350-F, and for the military temperature range (-55 ° C to + 125 ° C) specify S8X350-F. FEATURES • On-chip address latches • 3-state outputs • Schottky clamped TTL • Internal control logic for 8X300 system • Directly interfaces with the 8X300 bipolar microprocessor with no external logic • May be used on left or right bank ABSOLUTE MAXIMUM RATINGS PARAMETER1 F = Cerdip RATING UNIT APPLICATIONS • 8X300 working storage VCC VIN Supply voltage Input voltage +7 +5.5 Vdc Vdc VOH Vo Output voltage High Off-state +5.5 +5.5 Vdc TA Temperature range Operating N8X350 S8X350 o to +75 -55 to +125 °c TSTG Storage -65 to +150 TRUTH TABLE Note X = Don't care BLOCK DIAGRAM MODE ME SC WC MCLK BUSSED DATAl ADDRESS LINES Hold address Disable data out 1 X X X High Z MEMORY CELL MATRIX 32 x 64 = 2048 Input new address 0 1 0 1 Hold address Disable data out 0 1 0 0 Hold address Write data 0 0 1 1 Hold address Disable data out 0 0 1 0 Address High Z High Z Data in High Z MCLKo-----. SC O---__._--+--I COLUMN SELECT READ/WRITE CIRCUIT Hold address Read data 0 0 0 X Undefined state 12 0 1 1 1 Data out - we o---+---+-......... -r-, Hold address 12 Disable data out 0 1 1 0 High Z !ii!lDotiC!i 3
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
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Xl _Il_n_r Not. 2 RESUME NORMAL OPE
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Normally, the instruction cycle tim
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LB/RB del~ (TIIBS) or the delay tim
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Table 2-4. Bit Manipulation Functio
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The following sections provide gene
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6.154 MHz CLOCK NOMINAL r-----....
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\Nhen interfacing program storage c
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2.4.2 I/O Interface Typical interfa
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The preceding descriptions should n
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~ SIGNETICS 8X32 1/0 PORT - LB -- .
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stored in the successi ve-approxima
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g) Priority logic - If more than on
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~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117: -- u Current-Controlled Oscillator
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146: DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148: APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150: 8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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