8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

ADDRESS: Instruction address output signals. The opening and
closing of the internal address latches (register) occur, respectively,
with the leading and trailing edges of the third quarter-cycle.
Therefore, these latches are open only during the third
quarter-cycle. The address of the previous instruction cycle
remains stable until the trailing edge of the second quarter-cycle,
after which time a new address becomes available on the bus. The
point at which the new address becomes valid and stable is
dependent on the worst case condition of the following
considerations:
1. The propagation delay from the address latch input to the
address latch output, when the address latch starts to open
during the third quarter-cycle (T AS).
2. The propagation delay from the time an instruction becomes
stable to the address output (for example, a JMP instruction)
(TIA).
3. The propagation delay from the beginning a valid I/o bus input
to the address output (TI V A). As an example, an instruction in
which bit seven of the selected right bank device is examined
and the next instruction is executed if the bit is zero, or the
instruction at the current location plus fi ve is executed if the
bit is one (NZT RB7, *+5).
INSTRUCTION: Input signals to the instruction latches (register).
These latches are open for the duration of the first quarter-cycle
only. When considered at the chip level, there is a minimum set-up
and hold time requirement with respect to the trailing edge of the
first quarter-cycle. At a system level, there are further
requirements as to when and how long the-.illstruction inputs must be
valid. As is shown in Figure 2-16, the LB/RB signals are derived
directly from the instruction input during the input phase.
To insure the correct LB/RB signals, the instruction input must be
stable until the end of the input phase. Since the address bus is
stable for the entire input phase, the instruction output of the
program storage should be stable for the entire lill>ut phase, thus
satisfying the requirements for stability of the LB/RB signals.
Another factor determining the latest point at which the instruction
must become vali d is the worst case I/O input set-up time, as shown
below:
I/O - data stability depends on the setting of the LB/RB control
lines which, in turn, depend on the stability of the instruction bus.
See section on "Timing Considerations" for detailed explanation.
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