8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

INSTRUCTION •••• tI
INPUT
INSTRUCTION
LATCH
OUTPUT
PHASE
LB/RB
FIRST
QUARTER-CYCLE ______ --1
INPUT -
PHASE
..... _"
--
Figure 2-16. LB/RB Enable Paths
SC/WC: Select command and Write command signals. These signals
change state at the leading edges of the first and third
quarter-cycles. Keep in mind that SC and WC are never
concurrently in a high state.
LB/RB: The complementary left bank and right bank enable
signals. When required to change during the input phase, LB/RB
becomes valid after the latest occurance of either the leading edge
of the first quarter-cycle (TIBS) or the beginning of a valid
instruction (TIIBS). If a change is required during the output phase,
LB/RB is valid after the leading edge of the third quarter-cycle.
Refer to Figure 2-16.
I/o Bus: Input/Output Bus. The I/O bus input latches and the ALU
input latches are open during the first two quarter-cycles. Allowing
some delay after the leading edge of the third quarter-cycle, the I/O
bus drivers are turned on, and remain on throughout the fourth
quarter-cycle. When operating at 250 nanosecond instruction cycle
times, the I/O data may not be valid until the fourth quarter-cycle.
HAL T: Halt Signal. The HALT signal is sampled by': the 8X300
internal logic during the first quarter-cycle. If the HALT signal
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