8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

2.4.2 I/O Interface
Typical interfaces to the aX300 employ the aX32 latched
addressable bidirectional I/O port. This device provides a single
connection between the aX300 I/O bus and the user status and data
lines. A unique feature of this I/o port is the way in which it is
addressed. Each I/o port has an a-bit, field programmable address,
used to enable the device. When the SC signal is high, data at the
microprocessor port is treated as an address. if the address matches
the I/O port's internally programmed address, the I/O port is latched
into a selected state. The port remains selected until an address
which does not match its internal address is presented, at which
time the port is disabled. This feature eliminates the need for the
additional hardware required for port enable decoding. The a-bit
address field, combined with the LB/RB select bits, allow selection
of one of a possible 512 I/O ports.
The only disadvantage of this device is the increase in software
overhead and throughput time encountered when addressing is
necessary. Faster I/O selection may be implemented by adding bits
to the instruction word, similar to that which was done in Figure
2-21. This technique, illustrated in Figure 2-24, allows an I/O port
to be selected within the same instruction where it is used. By
eliminating the need for the I/O port select instruction, important
processor time is saved.
The program memory extension is followed by D-type latches, and
the latches in turn followed by a decoder. The outputs of the
decoder, ANDed with the bank select signal, comprise the I/O port
select circuitry.
ME
1/0
PORT
BIT N
BIT 1
}
EXTRA BITS ADDED
FOR FAST SelECT
ME
1/0
PORT
BANK SelECT
16
INSTRUCTION __ --1--1
ROM
1/0
BUS
8X300
13
ADDRESS I--+---'~I
Figure 2-24. Fast I/o Select For Small Systems
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