8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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BUS INtERfACE REGISTER ARRAY PRELIMINARY IWi21 BIPOLAR LSI DIVISION ffi > w GND 1 :: 3 D5A r DMAE 2 :::· 1 D1A 9 DOA 10 8X320 BUS INTERFACE REGISTER ARRAY I/) ~ 01/) ow °8 c PIN NO. PARAMETER 1,20 GND Ground 2 DMAE Direct Memory Access Enable 3-18 DOA-D7AI Primary Data Port DOB-D7B '- 19 ME Master Enable 21 MCLK Master Clock 22 SC Select Command 23 WC Write Command 24-31 IVO-IV7 Secondary Data Port 32 WS Write Strobe 33 RIW Read I Write Control 34 PiCE Programmed 110 Enable 35-38 AO-A3 Primary Port Address Select 39 B/W Byte I Word 40 VCC Power Circuit ground. FUNCTION Enables primary port to facilitate DMA transfers; does not affect secondary port. Sixteen 3-state lines used for data transfers to-and-from the primary data port; most significant bit is DOA and least significant bit is D7B. Enables secondary port when active low (ME). When MCLK is highj and 8X320 is enabled (ME), a register location may be either selected or written-into under control of SC and WC. With SC high, WC low, MCLK high and ME low, data on IVO through m is interpreted as an address. If anyone of the 16 register addresses (608-778) matches that on the 1/0 (IV) bus, that particular register is selected and remains selected until another address on the same bank (i.e. ME = low) is output on the 1/0 bus-at which time, the old register is deselected and a new register mayor may not be selected. With WC high, SC low, MCLK high, and ME low, the selected register stores contents of IVO-IV7 as data. Eight 3-state lines used to transfer data or 110 address to-and-from the secondary data port;· most significant bit is IVO and least significant bit is M. When active high, data appearing at the primary port (DOA-D7 A/DOB-D7B) is stored in the register array if the primary port is in the write mode. When this signal is high, primary port is ,in read mode; when signal is low, primary port is in write mode. When active low, primary port operates in programmed input I output mode with register to be read-from or written-into selected by AO-A3. Selects register or register-pair that primary port is to read-from or write-into. Most significant t;»it is A3; least significant bit is AO. When Signal is high, the primary port operates in the byte (8-bit) mode; when Signal is low, the primary port operates in the word (16-bit) mode. +5 volts. <strong>Al</strong>l barred symbols (OMAE. etc.) denote signals that are asserted (or active) when low (logical 0); signals that are not barred are aSlerted in the .tligh state (logical 1). 4 Si!jII!IICS
81320 PRELIMINARY OPERATING CHARACTERISTICS Memory Organization Memory and address correlation for the 16-register array is shown in Figure 2. From the primary port, the sixteen a-bit registers can be addressed in either byte (a-bit) or word (16-bit) format; in the word mode, the registers are addressed in pairs-Oa/1a, 2a/3a, 4a/5a, . .. 14al 15a, and BIPOLAR LSI DIVISION 16a/17a. From the secondary port, all registers are addressed in byte format-60a through 77 a. The memory consists of two a-bit flag registers and fourteen a-bit generalpurpose registers. The flag registers facilitate information transfers between the two ports and, in addition, they protect certain registers from being written into from the primary port. SECONDARY PORT MSB LSB iVa iV7 j j FLAG REGISTER 11001111 SECONDARY PORT ADDRESS = 608 - PRIMARY PORT ADDRESS 08 11001110 GENERAL PURPOSE REGISTER 11001101 _ SECONDARY PORT ADDRESS = 628 11001100 PRIMARY PORT ADDRESS = 28 GENERAL PURPOSE REGISTER 11001011 _ SECONDARY PORT ADDRESS = 648 11001010 PRIMARY PORT ADDRESS = 48 GENERAL PURPOSE REGISTER 11001001 _ SECONDARY PORT ADDRESS = 668 PRIMARY PORT ADDRESS = 68 MSB LSB A3 AO j j BYTE MODE 10000 FLAG REGISTER WORD MODE OOOX II SECONDARY PORT ADDRESS 61 8 BYTE MODE PRIMARY PORT ADDRESS - 18 0001 .. GENERAL PURPOSE REGISTER II SECONDARY PORT ADDRESS - 638 PRIMARY PORT ADDRESS = 38 ~ ::: ~0011 0100 L GENERAL PURPOSE REGISTER: l II I SECONDARY PORT ADDRESS - 658 r 010X LPRIMARY PORT ADDRESS - 58 1--.:- 0101 GENERAL PURPOSE REGISTER 011X 11001000 --------------_II.~SE~C~O~ND~A~RY~P~O~R!..T ~AD~D~RE::S~S..:=~6~78!!._ __...j___L PRIMARY PORT ADDRESS = 78 ~ 0111 GENERAL PURPOSE REGISTER ~---------------~ 11000111 _ SECONDARY PORT ADDRESS = 708 PRIMARY PORT ADDRESS 108 .. 1000 11000110 _______________ GENERAL PURPOSE REGISTER L 0110 GENERAL PURPOSE REGISTER 1 l 100X .... ~I;SE~C::O=;ND;A;RY;;P~O:R;T ;AD;:D;;RE:.:S~S~-~7~18!!.---_I f LPRIMARY PORT ADDRESS - 118 I~ 1001 11000101 _ SECONDARY PORT ADDRESS = 728 PRIMARY PORT ADDRESS = 128 11010 GENERAL PURPOSE REGISTER 101X II SECONDARY PORT ADDRESS = 738 11000100 ---------------_.~~~~~;;~~~~--__I PRIMARY PORT ADDRESS = 138 1011 GENERAL PURPOSE REGISTER 11000011 _ SECONDARY PORT ADDRESS = 748 PRIMARY PORT ADDRESS = 148 1 GENERAL PURPOSE REGISTER II SECONDARY PORT ADDRESS = 758 11000010 ------------------_.~~~~~~~~~~--__I PRIMARY PORT ADDRESS = 158 GENERAL PURPOSE REGISTER 11000001 -SECONDARY PORT ADDRESS = 768 PRIMARY PORT ADDRESS 168 .. I GENERAL PURPOSE REGISTER 11000000 II I SECONDARY PORT ADDRESS 778 L PRIMARY PORT ADDRESS = 178 1100 110X 1101 11110 111X 1111 PRIMARY PORT 1 ......----- EVEN ADDRESSES -----111..... 1------- ODD ADDRESSES ----....,....... 1 Figure 2. Memory and Address Organization tor the 8X320 Sl!IDOliCS 5
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
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Xl _Il_n_r Not. 2 RESUME NORMAL OPE
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Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146: DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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