8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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113UI BIPOLAR LSI DIVISION ARCHITECTURAL OVERVIEW The Signetics 8X300 Microcontroller (Figure 1) is a highspeed bipolar microprocessor implemented with low-power Schottky technology. The 8X300 brings together all the qualities needed-SPEED, FLEXIBILITY, and ECONOMYfor systems design in the many areas that require reliable bit stream management. Considerl-5V operation. TTL bus compatibility, and an on-chip clock-the result, a system with fewer parts. Considerl-the inherent power of LSI logic (programmable Rotate, Mask, Shift, and Merge functions in the data-processing path) and the ability to Fetch, Decode, and Execute a 16-bit instruction in a minimum of 250- nanoseconds-the result, a system with superior bit handling capabilities. Considerl-the 250ns cycle time in conjunction with extended microcode-the result, the flexibility of bit-slice devices with the programming ease of MOS microprocessors. Now, consider the results!----a device tailored to bit-stream management in the areas of Industrial Control, Input/Output Control, and Data Communications. The 8X300 uses three separate buses-one for 13-bit instruction addresses, one for 16-bit instructions, and a bidirectional 8-bit input / output data bus; except for the I/O bus, there are no time multiplexing of functions. PIN CONFIGURATION FEATURES • Fetch, Decode, and Execute a 16-blt Instruction in a minimum of 2SQ-nanoseconds (one machine cycle) • Bit-oriented Instruction set (addressable single-ormultiple bit subflelds) • Separate address, instruction, and I/O buses • Source/destination architecture • On-Chip oscillator and timing generation • Eight a-bit working registers • TTL inputs and outputs • BIPolar Low-Power Schottky technology • 3-State I/O bus • Single +SV supply ORDERING INFORMATION Commercial Order number: N8X3001 Packaging information: Refer to Signetics price list Supply voltage: 5V (± 5%) Operating temperature range: O°C to +70°C Military Order number: S8X300-1 Packaging information: Refer to Signetics price list Supply voltage: 5V (± 5%) Operating temperature range: -40°C to + 100°C Order number: S8X300-2 Packaging information: Refer to Signetics price list Supply voltage: 5V (± 10%) Operating temperature range: -20°C to + 100°C 4 1i!lIOliCIi
BIPOLAR LSI DIVISION PROGRAM STORAGE (READ-ONLY MEMORY)-BK X lS ROM/PROM * ________ •• ~ NOTE Up to 256 bytes can be directly interfaced to eBch bank. With decoders and some externBI logic, the 110 complement can be expanded to the point of critical timing. r--~~~~~;::g~--l L~~~!~~~~~~~~ 1 VCR VR~ ---{I A7 ASiID--- --IT AS A9~ --IT A5 A 10 £J-- RAM DATA - STORAGE (128 XB) ---[[ A4 All iID-- ----{I A3 A12 ~ --IT A2 HALT N---)' USER _ r.;- ~ CONTROLLEO -"L.!. Al RESET ~, INPUTS I-OF-12B ----cr: AO XTAL ::E Xl ffi iVa tEl-- r ~ (OFF-CHIP) IT!: X2 g iV1 '4ol- - 8~ :==.r @ GND ~~ iV2~ ---IT! 10 CD~ iV3~ -IE 11 ~ VCC ~ _.iII._ _ .............. ~-~ 12 W4~ -ill: 13 ~14 iV6EJ- MCLK ~'-'-----:------I.-lS/fTO PORTS iV5 tID- ~ 15 iV7rm-- ~IS f----m: 17 Ritm-- [B :m.-.----' ~IB WC~.-.-----~ ~19 SC~'-'------' f-@ 110 115 :ill- ~Ill 114m- ~112 113~ ..... .. 1-OF-12 1/0 PORTS RAM DATA STORAGE (12B X 8) LEFT BANK NOTE RIGHT BANK PIN NO. IDENTIFIER 2-9/45-49 A0-A12 13-28 10-115 33-36 IV0-IV7 38-41 10 & 11 Xl & X2 42 MCLK 30 WC 29 SC 31 LB 32 RB 43 RESET 44 HALT 50 VR 1 VCR 12 GND 37 Vcc NAME AND FUNCTION Program Address Lines: These outputs permit direct addressing of up to 8192 words of program storage. A high voltage level equals a binary "1"; A12 is Least Significant Bit. Instruction Lines: These input lines receive 16-bit instructions from program storage. A high voltage level equals a binary "1"; 115 is Least Significant Bit. Input/Output Bus: These bidirectional three-state lines communicate with up to 5121/0 devices (256 per bank). A low voltage level equals a binary "1"; IV7 is Least Significant Bit. Connections for a capacitor, a series-resonant crystal, or an external clock source with complementary outputs. For precise frequency control, a crystal or external source is required. Master Clock: This output is used for clocking 1/0 devices andlor synchronization of external logic. Write Command: When signal is high (binary 1), data is being output on pins IV0-IV7 of 1/0 bus. Select Command: When signal is high (binary 1), an address is being output on pins IV0-IV7 of I/O bus. When the LB signal is low (binary 0), anyone of up-to-256 110 devices (or memory locations) in the left bank can be accessed. When the address of a particular device (or memory location) matches the address on the IV bus, that particular device (or memory location) is enabled and selected for input I output operations. A" addresses on the left bank that do not match are deselected. When the RB signal is low (binary 0), anyone of up-to-256 110 devices (or memory locations) in the right bank can be accessed. When the address of a particular device (or memory location) matches the address on the 110 bus, that particular device (or memory location) is enabled and selected for input loutput operations. A" addresses on the right bank that do not match are deselected. When reset input is low (binary 0), the microcontro"er is initialized-sets Program Counter I Address to zero and inhibits MCLK output. When halt input is low (binary 0), internal operation of microcontro"er stops at the start of next instruction. The stop function does not inhibit MCLK or affect any internal registers. Internally-generated reference output voltage for external series-pass transistor. Regulated voltage input from series-pass transistor (2N5320 or equivalent). Circuit ground. Input connection for +5V power. Figure 2. Typical 8X300 System with Pin Definitions !ii!lIOliCI ACTIVE STATE High High Low - High High High Low Low Low Low - - - - 5
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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