8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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BIPOLAR LSI DIVISION Crystal Timing: When a crystal is used, the on-chip oscillator operates at the resonant frequency (fo) of the crystal; the series-resonant quartz crystal connects to the aX300 via pins 10(X1) and 11 (X2). The lead lengths of the crystal should be approximately equal and as short as possible; also, the timing circuits should not be in close proximity to external sources of noise. The crystal should be hermetically sealed (HC type can) and have the following electrical characteristics: Type: Fundamental mode, series resonant Impedance at Fundamental: 35-ohms maximum Impedance at Harmonics and Spurs: 50-ohms minimum The resonant frequency (fo) of the crystal is related to the desired cycle time (T) by the equation fo = 2/T; for a cycle time of 250 ns, fo = aMHz. Using an External Clock: The aX300 can be synchronized with an external clock by simply connecting appropriate drive circuits to the X 11 X2 inputs. Figure 7 shows how the on-chip oscillator can be driven from the complementary outputs of a pulse generator. In applications where the microcontroller must be driven from a master clock, the X 11 X2 lines can be interfaced to TTL logiC as shown in Figure a. PlA.SE GENERATOR PULSE GENERATOR CHARACTERISTICS: ZOUT = soo RISETIME ""lo,.,SEC + X=IL..I1..JL 1 I I I I I I son I I I I I I l1- 8X300 MICROCONTROLLER : son - X2=~ VOUT = ()'1 VOLT SKEW ""10n. CLOCK - ...... ... ...... .... Xl=-fl--fl--{l- Vcc • 1K I I I I I I ~ 8X300 . MICROCONTROLLER lK • = OPEN COLLECTOR TTL DRIVER CHARACTERISTICS: FALL TIME ""lo,.,SEC SKEW BETWEEN COMPLEMENTARY OUTPUTS ""10n. X2=~ Figure 7. Clocking with a Pulae Generator Figure 8. Clocking with TTL RESET LogiC The R'E"SET line (piri 43) can be driven from a high (inactive) state to a low (active) state at any time with respect to the system clock, that is, the reset function is asynchronous. To ensure proper operation, the RESET line should be held low (active) for one full instruction time. When the line is driven from a high state to an active-low state, several events occur-the precise instant of occurrence is basically a function of the propagation delay for that particular event. As shown in the acompanying RESET timing diagram, these events are: • The Program Counter and Address Register are set to an all-zero configuration and remain in that state as long as the Fi"ESEfline is low. Other than PC and AR, reset does not affect other Internal registers. • The Input/output (IV) bus goes three-state and remalnsln that mode as long as the RESET line Is low. • The Select Command and Write Command Signals are driven low and remain Inactive as long as the RESET line islow. • The Left Bank/Right Bank signals are undefined for the period In which the JfESEf line is low. During the time RES"Ef is active-low, MCLK is inhibited; moreover, if the RESE"f line is driven low during the last two quarter cycles, MCLK can be shortened for that particular machine cycle. When RESET line is driven high (inactive) one-quarter to one full instruction cycle later-MCLK appears just before normal operation is resumed. The RESET IMCLK relationship is clearly shown by "B" in the timing diagram. As long as the RESET line is active-low, the HALT signal (described next) is not sampled by internal logic of the aX300. HALT Logic The HALT signal is sampled via internal chip logic at the end of the first internal quarter of each instruction cycle. If, when sampled, the HALT signal is active-low, a halt is immediately executed and the current instruction cycle is terminated; however, the halt cycle does not inhibit MCLK nor does it affect any internal registers of the aX300. As long as the HALT line is active-low, the SC and WC lines are low (inactive) and the input 1 output (IV) bus remains in the three-state mode of operation. The halt cycle continues until, when again sampled, the HALT line is found to be high; at this time, normal operation is resumed. Timing for the halt signal is shown in the accompanying diagram. 20 !itgnOliCG
UICIOGONTIOLLEI BIPOLAR LSI DIVISION RESET TIMING DIAGRAM Xl_ RESUME NORMAL OPERATION t Not. 2 AO-A12 _ L scawc_ MCLK_ NOTES 1. A High to Low transition of the RESET signal will force the Address Bus to an all-zero 2. The REm signal can switch from Low to High at any point within this time interval and, configuration. in all cases, MCLK will occur at least one-quarter cycle time later as shown. HALT TIMING DIAGRAM :- HALT CYCLE -I I 4 I 4 Xl HALT--------~::' ~~~~:::_::~~~~ II -I I..-THH 1 I Note 1 THS_I 1- I Note 2 I ~---....-J'~---~ """""""'" I r-r-rrrrrrrrrrrrr,r------------- \\\\\\\\\\\\\\\\'l ,/ /////////////// \\\\\\\\\\\\\\\\\ /I /////////////// '-'-'-'-'-'-'-'-'-'-'-'-'-'-'-1'-'---" t'-' J.../.../.../../.../.../JJ../.../.../.../ I I I-I I 1- scawc----------'~"''_ __________ ~~ :\ ~ I '----------------------------~ I MCLK NOTES 1. The HALT signal can switch from High to Low at any time during this interval. THH-hold time from Xl to RAi:f (independent of instruction cycle time) 2. The HALT signal can switch from Low to High at any time during this interval. Timing Descriptions: THS-set-up time from HALT to Xl (independent of instruction cycle time) TMHS-set-up time from MCLK to RAi:f (dependent upon instru~tion cycle time) TMHH-hold time from MCLK to RAi:f (dependent upon instruction cycle time) sagOOliCIi 21
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8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91: BIPOLAR LSI DIVISION Internal Timin
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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