8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

I BIT I ITCHED IODRESSABLE BIDIRECTIONAL 110 PORT
~
IT32/1T33z1135/IT36
IXli,'IX36,IX42
BIPOLAR LSI DIVISION
AC ELECTRICAL CHARACTERISTICS O°C:5 T A:5 70°C, VCC = 5V ± 5%
PARAMETER
INPUT
TEST
CONDITION
Min
LIMITS
Typ
Max
UNIT
tpo User data delay (Note 1 )
UO X
MCLK*
BICt
C L = 50pF
25 38
45 61 ns
40 55
tOE
User output enable
BOC
C L
= 50pF
18
26 47 ns
too User output disable
BIC
BOC
C L
= 50pF
18
16
28 35
23 33
ns
tpo J.1P data delay (Note 1)
IV X
MCLK
C L = 50pF
38 53
48 61
ns
tOE
J.1P output enable
ME
SC
WC
C L = 50pF
14
19 25 ns
too J.1P output disable
ME
SC
WC
C L = 50pF
13
17 32 ns
tw
Minimum pulse width
MCLK
BICt
40
35
ns
tSETUP
Minimum setup time
UO XD
BIC*
IV X
ME
SC
WC
I
(Note 2)
15
25
55
30
30
30
ns
t HOLD
Minimum hold time
UO XD
BIC*
IV X
ME
SC
WC
(Note 2)
25
10
10
5
5
5
ns
• Applies for 8T32, 8X32 and 8T33 only.
t Applies for 8T35, 8T36 and 8X36 only.
o Times are referenced to MCLK for 8T32, 8X32 and 8T33, and are referenced to BTC for
8T35, 8T36 and 8X36.
NOTES:
1. Data delays referenced to the clock are valid only if the input data is stable at the arrival
of the clock ana the hold time requirement is met.
2. Set up and hold times given are for "normal" operation.BTC setup and hold times are for
a user write operation. SC setup and hold times are for an I/O Port select operation. WC
setup and hold times are for a Microprocessor Bus write operation. ME setup and hold
times are for both IV write and select operations.
6 Si!lnotics