8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

The Program Address logic data flow is shown in Figure 2-4. When
operating with instructions other than Program Control instructions,
the Program Counter data is incremented by the Increment logic
during the third quarter-cycle. The incremented data then passes
through the lower ports of Multiplexers A, Band C, and is loaded
into the address Register. During the fourth quarter-cycle this new
address is looped back and loaded into the Program Counter.
The above described data flow becomes altered when operating with
Program Control instructions (XEC, NZT, JMP). In these cases, the
lower five or eight bits of the address are received from the ALU
via the upper ports of Multiplexers A and B. In the case of the JMP
instruction, the upper five bits of the address are received from the
instruction register through the upper ports of Multiplexer C. The
JMP instruction is unconditional and is immediately loaded. In the
case of the NZT instruction, the source is first tested for non-zero
contents. If the non-zero condition (A=/O) exists the new address is
loaded, otherwise normal program sequencing continues. The XEC
instruction differs in that the new address in the Address Register is
not looped back to the Program Counter. The result is that unless a
JMP is encountered at the executed instruction, the program
sequencing resumes operation at the address following the XEC
instruction. That is, the program counter, which still contains the
address of the XEC instruction, is incremented as normal.
2-6