8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

2.2 8X300 TIMING
To understand the 8X300 timing, it is necessary to know when the
internal latches of the device are open and when they are not.
Figure 2-11 is a detailed internal block diagram of the 8X300,
depicting the latches and registers referred to in the discussions
that follow in this section of the manual. Figure 2-12 is a timing
chart illustrating the actions of these latches and registers
throughout an instruction cycle. Table 2-3 describes the timing
specifications of the device. It should be noted that all 8X300
internal latches are level triggered.
2.2.1 Instruction Cycle
The Internal Timing Generator of the 8X300 is depicted in Figure
2-13. Either an external TTL clock or a crystal may be connected
to Xl and X2, the inputs to the device's internal oscillator. In
conjunction with the sequencer, the output of this oscillator
generates all internal timing-control signals. Figure 2-14 shows the
relationship of the internal timing signals to the Xl input.
The 8X300 instruction cycle comprises four transitions of the
internal system clock. The internal latches are controlled by these
transisions, commonly referred to as quarter-cycles. Keep in mind
that "quarter-cycles" refer to transitions of the internal system
clock, not transitions of Xl.
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