- Page 1: 8H500 DESIGn GUIDE Smn~liCS a subsi
- Page 5 and 6: CONTENTS Chapter Page Preface .....
- Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
- Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
- Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
- Page 13 and 14: 1.2 DESIGN AD V ANT AGES OF THE SIG
- Page 15 and 16: In the area of development systems,
- Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
- Page 19 and 20: The function of the operand fields
- Page 21 and 22: The Program Address logic data flow
- Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
- Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
- Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
- Page 29 and 30: The second, and most desirable, met
- Page 31 and 32: 2.2 8X300 TIMING To understand the
- Page 33 and 34: XI ~~------------------------------
- Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
- Page 37 and 38: 2.2.2 Timing Calculations It is an
- Page 39 and 40: INSTRUCTION •••• tI INPUT I
- Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
- Page 43 and 44: Normally, the instruction cycle tim
- Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
- Page 47 and 48: Table 2-4. Bit Manipulation Functio
- Page 49 and 50: The following sections provide gene
- Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
- Page 53 and 54:
\Nhen interfacing program storage c
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2.4.2 I/O Interface Typical interfa
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The preceding descriptions should n
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~ SIGNETICS 8X32 1/0 PORT - LB -- .
- Page 61 and 62:
stored in the successi ve-approxima
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g) Priority logic - If more than on
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~LK------------------------~ +S~ 1
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2.5.2 Interrupt Control (Handshake)
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The positive edge of the INTERRUPT
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the writing of I/O addresses is inh
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The outputs of the flip-flops are u
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10 11 12 SHIFT LOGIC MERGE LOGIC 13
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BIPOLAR LSI DIVISION PROGRAM STORAG
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BIPOLAR LSI DIVISION phase. During
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MIEIOEO" 11011 fR 81311 AND-data in
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MICRacalTRaLLER 8X311 BIPOLAR LSI D
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BIPOLAR LSI DIVISION AC CHARACTERIS
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111£60£uNJIOLLER 11300 BIPOLAR LS
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: ... BIPOLAR LSI DIVISION 8X300 TI
- Page 91 and 92:
BIPOLAR LSI DIVISION Internal Timin
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UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
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BUS IN I EkEICE lEGIS I EI IkklY PR
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81320 PRELIMINARY OPERATING CHARACT
- Page 99 and 100:
BUS IN I EIEICE lEGIS I EI lIllY PR
- Page 101 and 102:
PRELIMINARY elPOLAR LSI DIVISION AC
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BIPOLAR LSI DIVISION ARCHITECTURAL
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BIPOLAR LSI DIVISION SYSTEM INTERFA
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BIPOLAR LSI DIVISION Command/Status
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FLOP" DISI FOR.III EN/CONTROl I FR
- Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
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BIPOLAR LSI DIVISION DC CHARACTERIS
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~ FLOPPY DISK FORMATTER fGONTROLLER
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-- u Current-Controlled Oscillator
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2048 BII BlrOtliliM (25618) PRELIMI
- Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
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PRODUCT DESCRIPTION Both the 8T31 a
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8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151