8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

BI))U
BIPOLAR LSI DIVISION
DC CHARACTERISTICS vee = 5V (±5%), TA = ooe to 70°C
PARAMETER
TEST CONDITIONS
LIMITS
Min Typ Max
UNITS
COMMENTS
VIH High level input voltage 2.0 VCC V For all inputs except X 1, X2,
VIL Low level input voltage -1.0 .S V
C1, C2, CCO, and VCR
Vce Supply voltage 4.75 5.0 5.25 V 5V (±5%)
VCR Regulator voltage VCC = 5V 3.1 V From series-pass transistor
VCL Input clamp voltage VCC = Min -1.0 V Inputs X1, X2, C1, C2, and CCO
liN = -5mA
do not have internal clamp
diodes.
VOH High level output voltage VCC = Min; 2.7 V DC 1 through DC7 (Pins 6-12) &
IOH = -0.4mA OW (Pin 4)
VCC = Min; IOH = -3m A 2.4 V IVO-IV7 (Pins 25-32)
VOL Low level output voltage Vec = Min; 0.5 V DC1 through De7 (Pins 6-12);
IOL = SmA
PUP, PDN (Pins 33,34); OW
(Pin 4)
Vec = Min; IOL = 16mA 0.55 V IVO-IV7 (Pins 25-32)
VCC = Min; IOL = 40mA 0.55 V WG (Pin 19)
ICEX Open-collector leakage Vec = Min; 100 #LA WG (Pin 19); PUP (Pin 34);
current with output set to 1. VOUT = Vce PDN (Pin 33)
IIH High level input current VCC = Max; VIN = 2.7V 20 #LA DS1-DS5 (Pins 13-17);
PF (Pin 1S); DR (Pin 5)
Vee = Max;
VIN = 5.25V;
ceo (Pin 35) input 1 4 rnA
current = OmA
Vec = Max; VIN = 5.25V
ceo (Pin 35) input 0 2 rnA
current = 1 rnA
40 #LA ME (Pin 21); MCLK (Pin 22);
SC (Pin 23); WC (Pin 24)
With C 1 (Pin 36) under test, C2
(Pin 37) is open and, vice-versa.
-"
""
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Vec = Max; 1 4 rnA With X 1 (Pin 2) under test, X2
VIN = 0.6V
(Pin 3) is open and, vice-versa.
V CC = Max; VIN = 4.5V 50 #LA IVO - IV7 (pins 25-32)
VCCO Input voltage for VCC = 5V; TA = 25°C 750 mV
current-controlled
oscillator
CCO input current
(Pin 35) = 300 #LA
12 sagOOliCS