8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

1. ~elect ~ommand (SC) - a high (binary 1) on this line indicates
that an address is being output on the I/O bus.
2. ~ite ~ommand (WC) - a high (binary 1) on this line indicates
that data is being output on the I/o bus, to be stored in the
previously enabled register/port.
NOTE: When both SC and WC are low (binary 0) the
Microcontroller expects data from the selected device. Both
SC and WC high (binary 1) is a condition not generated by the
Microcontro ller.
3. Left Bank Select (LB) - a low (binary 0) on this line enables
one of two groups of I/o devices (or memory locations). In all
following text, this group of Memory-I/O devices is referred to
as the Left Bank.
4. Bight ~ank Select (RB) - a low (binary 0) on this line enables
the second of the previously mentioned two groups of I/O
devices (or memory locations). In all following text, this group
of Memory-I/O devices is referred to as the Right Bank.
NOTE: LB and RB are complementary outputs of a single
control line which can be considered as a ninth address bit.
EactLj/O ~vice (port, memory, etc.) is connected to either
the LB or RB control line.
5. Master Clock (MCLK) - an output signal of the Microcontroller
used for clocking of I/O devices and/or synchronization of
external logic. The I/o bus data must be stable during the
period the MCLK is high.
Figure 2-5 illustrates a simple control system composed of the
Signetics 8X300 and its compatible devices. The illustration depicts
the wiring configuration of the Program Address, Instruction and I/O
buses, and the control lines. In this particular application the Left
Bank of devices is composed of I/O ports used for interface with
user equipment. The Right Bank of devices comprise the system's
external Working Storage. Through program control, the
Microcontroller is able to input data from one bank of devices,
manipulate this data and output it to the opposite bank of devices,
all in one instruction cycle (see Figure 2-6). It should be noted
thatthe I/o and Memory devices must have been addressed prior to
this instruction cycle, and that an operation from one device to
another of the same bank is not normally done during a single
instruction cycle. It is a simple matter to input data from a specific
device, operate on it and output it again to the same device during
one instruction cycle.
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