8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge
8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge
8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge
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\-<br />
INPUT PHASE<br />
MCLK= LOW<br />
OUTPUT PHASE<br />
I MCLK = HIGH<br />
.. . ..<br />
..<br />
I<br />
INST AND<br />
I/O BUS<br />
DATA INPUT<br />
DATA<br />
PROCESSING<br />
ADDR AND<br />
I/O BUS<br />
CHANGING<br />
ADDR AND<br />
I/O BUS<br />
DATA VALID<br />
~1/4CYCLE~i--1/4CYCLE~~1/4CYCLE~1/4CYCLE_1<br />
_LB_/R_B __ -J)(~ __________________ J)(~ ________________ _<br />
I-~....---------- 250 ns ------------1-~1<br />
INST = INSTRUCTION<br />
MCLK = MASTER CLOCK<br />
RB = RIGHT BANK<br />
I/O = INPUT/OUTPUT<br />
ADDR = ADDRESS<br />
LB = LEFT BANK<br />
Figure 2-6. Instruction Cycle<br />
2.1.6 Bit Manipulation Logic<br />
The A input of the ALU is preceded by data-rotate and data-mask<br />
logic. The combination of right-rotate and mask functions allows<br />
selection of one or more bits from a source data field. For<br />
instructions where both the source and destination are internal<br />
registers, only the rotate function is available, the data being a<br />
fixed length of eight bits.<br />
The right-rotate function provides an end-around-shift of one to<br />
seven places of the 8-bit source field. In this manner, the least<br />
significant bit of the bit string required can be positioned in the<br />
least significant position of the data byte, ready for further<br />
processing. See Figure 2-7.<br />
2-10
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