8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

The RAM address latches must be sequentially loaded, the data
latch selected, then the data itself loaded into the data latch. If the
RAM array is composed of devices with an access time of 250
nanoseconds or less, the RAM address. will be stable by the time
data is to be written to or read from the RAM array.
The system designer must ensure that the program instruction
becomes valid early enough relative to MCLK in order for the RAM
address latch enable bits (116 and 117) to be latched into the
D-Iatches. In cases where the instruction is not yet valid at the
trailing edge of MCKL, the MCLK signal to the D-Iatches can be
slightly delayed by adding two or three buffer stages to the MCKL
signal line, just prior to the D-Iatches
AO-A12
(2)
LS363
OR
EQUIVALENT
...... PROGRAM
...,..
MEMORY
....... PROGRAM
..,..
MEMORY
EXTENSION
116
117
11S
119
... 1Vo-iV7 ..
...
SIGNETICS ,....---
SX300 sc
10-115 II.. MICROCONTROLLER LB
,..
~
WC
D
TYPE
LATCH
L--
LS375
OR
EaUIVALENT
MCLK
f---}USER
f--- OPTION
~
~
.-1--
..
"
OE
ADDRESS
HI
LATCH
E
~
:==J }-
-
.. ADDRESS
LO
,.
LATCH
DE
-b
1===rJ--
-
...t ~ SIGNETICS
.... ...,.. BT32
E
(S) ..
ADDR ...,..
HI
(S) ..
MOS
MEMORY
ARRAY
WITH
ADDR" DECODE
LO
(64K BYTES
MAX)
...t
(S) ......
..... DATA"""
I
r
Figure 2-21. Extended Microcode Select
2-37