8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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+5V PROGRAM STORAGE (ROM, PROM, OR RAM-TTL COM· PATIBLE, UP TO 8K BY 16 BITS) - HALT -- RESET AO-A12 VCC 10-115 .:.:.:.:.:.::::::::::::::::::.:::.:.:.:.:.:~ ..e- X1 -L X2 ."- .. '" ..... r;2N52~ ... .... VR 8X300 VCR IVO-IV7 SC WC MCLK - LB (NOTE) -RB 8X32 "" INPUT/OUTPUT ..... .... ~ PORT r-' ~ ..... "" t '"' - ,.. ... ,. WORKING STORAGE - (RAM) ~ - - - +- r-~ ... ll~ 8X32 "" INPUT/OUTPUT PORT ~. . ~ ~ .... ... TO EXTERNAL DEVICE ,.. LEGEN D: PORT INPUT CONTROL PORT OUTPUT CONTROL ~ = ADDRESS ............• : ~ = INSTRUCTION _ = DATA ... ,. TO EXTERNAl- DEVICE PORT INPUT CONTROL PORT OUTPUT CONTROL NOTE: UP TO 256 BYTES CAN BE DIRECTLY INTERFACED TO EACH BANK. WITH DECODERS AND SOME EXTERNAL LOGIC, THE I/O COMPLEMENT CAN BE FURTHER EXPANDED 1.3 DESIGN CONSIDERATIONS Figure 1-2. Typical System Block Diagram The Signetics 8X300 Microcontroller moves data at 4 million operations per second, while requiring only minimal support and peripheral circuitry. Where speed is of prime importance, the 8X300 offers an economic alternative to random logic or the bit-slice approach. The device reduces both the complexity and cost usually associated with the above mentioned approaches. Anywhere rapid intelligent control is important -- disk drive controllers, CRT displays, data communications, industrial control -- the 8X300 is an excellent choice. Signetics offers extensive support for the development of systems employing the 8X300. The designer will find aids available in the forms of: · Development Systems · Training · Documentation · Applications Support 1-5
In the area of development systems, Signetics offers an 8X300 Evaluation Kit and an 8X300 Microcontroller Cross Assembly Program (MCCAP). Training aids include a general introductory movie on the 8X300 and the 8X300 Training Course, a self-paced audio-visual course. A wide range of 8X300 Family documentation is available. In addition to application notes and data sheets for specific devices, Signetics offers the following manuals: - The 8X300 Design Guide - The 8X300 Programmi ng Manual - The 8X330 Floppy Disk Controller Manual - The Microcontroller Cross Assembler Program Manual During the design phase of a project, the Field Applications Engineer is an invaluable source of advice. They are available to offer on-site technical assistance, and are equipped technically to help analyze your application and transform it into a viable hardware/software system. The Field Applications Engineers are supported by the factory-based Product Applications Engineers, who are also available to answer specific technical questions regarding the use of the Signetics 8X300 and its support components. Additional design tools which are under development and will be released in the near future include - 8X300 In-Circuit Emulator - A hardware development system that converts other development systems and computers into 8X300 development systems. MDS MCCAP - A version of the 8X300 assembler tailored to execute on the MDS development system. PDP-II MCCAP - A version of the 8X300 assembler that executes on PDP-II and LSI-II computers. 8X300 Designers Kit - A new version of the current Evaluation Kit which includes writable program storage, an RS232 port, and an key/display panel. 1-6
Page 1 and 2: 8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4: SIGNETICS ® reserves the right to
Page 5 and 6: CONTENTS Chapter Page Preface .....
Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
Page 13: 1.2 DESIGN AD V ANT AGES OF THE SIG
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66:
~LK------------------------~ +S~ 1
Page 67 and 68:
2.5.2 Interrupt Control (Handshake)
Page 69 and 70:
The positive edge of the INTERRUPT
Page 71 and 72:
the writing of I/O addresses is inh
Page 73 and 74:
The outputs of the flip-flops are u
Page 75 and 76:
10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78:
BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80:
BIPOLAR LSI DIVISION phase. During
Page 81 and 82:
MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84:
MICRacalTRaLLER 8X311 BIPOLAR LSI D
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BIPOLAR LSI DIVISION AC CHARACTERIS
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111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90:
: ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92:
BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94:
UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96:
BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98:
81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100:
BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102:
PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104:
BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106:
BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108:
BIPOLAR LSI DIVISION Command/Status
Page 109 and 110:
FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
Page 113 and 114:
BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116:
~ FLOPPY DISK FORMATTER fGONTROLLER
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-- u Current-Controlled Oscillator
Page 119 and 120:
2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126:
8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
Page 131 and 132:
1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134:
BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136:
PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138:
PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144:
PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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