8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

~
2.1 CPU ARCHITECTURE
Figure 2-1 is a simplified block diagram of the Signetics 8X300
illustrating the major internal functional blocks and data paths of
the device. As is shown in the illustration, the device includes an
Arithmetic Logic Unit (ALU), eight 8-bit working registers, logic for
rotate and mask of data, logic for shifting and merging of data,
decode and control logic, an address register, a program counter and
an instruction register.
2.1.1 Decode and Control Logic
The decode and control logic contained in the Signetics 8X300
interprets the instruction according to its op code and operand
fields, and directs the device to perform the specified operation.
Additionally, the decode and control logic provides signals (Select
Command, Write Command, Left Bank/Right Bank) to control logic
external to the device. Such logic includes RAM and I/O interface
to user equipment. As shown in Figure 2-2, the decode and control
logic also receives control commands (RESET and HALT) from logic
external to the device.
INSTRUCTION
INPUT (16)
~
INSTRUCTION
REGISTER
OP
WORKING
CODE
,.
- STORAGE
--·
CONTROL
- } ROTATE
CONTROL
..
OPERAND (5)
....
FIELD
-
-'" } LENGTH
A ,. CONTROL
..
DECODE
} I/O
AND
CONTROL
CONTROL
LOGIC
·-
(3)
OPERAND .... --
~
FIELD
B ,.
- ALU
(3) .... - } INTERNAL
(5)
....
-
.. > CONTROL
-
- -'"
OPERAND
FIELD
sc
C ,.
WC
t t
'r--
~
LB
~>--
RB
>>--
HALT
RESET
:~
Figure 2-2. Decode and Control Inputs and Outputs
2-3