8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

\Nhen interfacing program storage composed of ROMs with an access
time greater than 80 nanoseconds, the problems facing the designer
are quite similar to those encountered when designing for slower
working storage. Often, the solution to the problem is the same for
both slower working storage and slower program storage. For
example, an instruction cycle time of 500 nanoseconds will allow the
designer to use either RAMs or ROMs (or both) having an access
time of 120 nanoseconds. A solution for slow RAM is that of
inserting software delays after each RAM address function. A
software delay can be generated by moving a register to itself - the
equivalent of a NOP. The drawback to using software delays is that
they increase the required program storage. If, due to generation of
software delays, program storage size becomes a problem, then the
designer might consider hardware generation of delays. Figure 2-22
illustrates a hardware implementation of a delay using a minimum
of additional devices.
This configuration is suitable for use with RAM devices having
access times of up to 250 nanoseconds. By increasing the number of
flip-flops, additional hardware delays may be added, based on the
RAM access time requirements.
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8X300
HALT
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74LS109
OR
EOUIVALENT
se 1------.... _ J
MeLKI----------~~~~e
r ..
-
K ___ O
vee
.. r--
MeLK~ ________ ~r__l~ ______ ~r__l~ ____ _
sc
H-A-LT ---------..... 1
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Figure 2-22. Hardware Delay Generation
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