8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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Table 2-5. 8X300 Compatible Devices Program Storage (ROM, PROM) Type Description Access Time 82523/123 825126/129 825131 825115 825137 825181 825185 825190/191 82S2708(Mil. only) OC/TS OC/T5 T5 T5 TS TS T5 OC/T5 T5 32X8 256X4 512X4 512X8 lKX4 1KX8 2KX4 2KX8 lKX8 PROM PROM PROM PROM PROM PROM PROM PROM PROM 50 ns 50 ns 50 ns 60 ns 60 ns 70 ns 100 ns 80 ns 60 ns Working Storage (RAM) 82509 82516 825116 8X350 OC TS TS TS 64X9 256Xl 256X1 256X8 RAM RAM RAM RAM 50 ns 50 ns 40 ns 35 ns I/O Devices 8T26A/28 8T31 8T32/33 /35 /36 8T39 8T58 8X41 8X320 Quad Bus Transceiver 8-Bit Bidirectional I/O Port 8-Bit Addressable Bidirectional I/O Port Bus Extender Transparent Bus Expander Bidirectional Bus Extender/Repeater Bus Interface Register Array Communications Devices 2652 8X01 8X330 9403 Synchronous Data Link Controller Cyclic Redundancy Checker Floppy Disk Formatter /Controller 64-Bit FIFO Buffer Memory Integrated Fuse Logic 825100/101 825102/103 T5/0C 16X8X48 FPLA OC/T5 FPGA 2-35
6.154 MHz CLOCK NOMINAL r-----.... [>~--.... ~ X1 X2 A B C 81.25 ns ~ 62.5 ns I- I ·1- I j.-- 18.75 ns ·1 81.25ns I I L I I I I L -i- ·1- 100ns ~ I I I L Figure 2-20. Elongated Positive Cycle Clock Figure 2-21 illustrates a system which operates with up to 64K bytes of industry standard, TTL compatible MaS working storage. The system is implemented through the use of some additional hardware. It should be noted that the program memory should consist of devices with an access time of 80 nanoseconds or less and that the instruction word has been extended from 16 bits to 20 bits. Two of these bits are used as enables for the RAM address latches. The remaining two bits may be used for other control or display drive functions. <strong>Al</strong>though this method requires additional ROMs for the extension, it eliminates the latch select instruction cycle that would be necessary if addressable latches, such as the 8X32, were used as RAM address latches. This saves both in program storage and in total processing time for working storage. It requires that a specific program structure be followed within program storage. 2-36
Page 1 and 2: 8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4: SIGNETICS ® reserves the right to
Page 5 and 6: CONTENTS Chapter Page Preface .....
Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14: 1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16: In the area of development systems,
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49: The following sections provide gene
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102:
PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104:
BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106:
BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108:
BIPOLAR LSI DIVISION Command/Status
Page 109 and 110:
FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
Page 113 and 114:
BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116:
~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118:
-- u Current-Controlled Oscillator
Page 119 and 120:
2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126:
8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128:
PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130:
113271]33/1135/1136 1I12jll16 1142
Page 131 and 132:
1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134:
BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136:
PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138:
PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140:
= SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144:
PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146:
DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148:
APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150:
8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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