8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

TIA + TACC ~ Instruction Cycle
thus,
T ACC s 250 nS - 170 nS
and,
T ACC:s 80 nS, confirming that a program
storage access time of 80 nanoseconds is satisfactory.
MCLK
,,-'" ~_J ! ii
I
I
:::, ~ i !'---+-i ---+E--:-'1:
I
tJtt
2 1 .1 II
I I :: I
:_"1 ":
[8, JIB I I I I:
I I I
iVii-M I I I I
I
I
1 MCLK to [l/JIB (Input
ph ••• ) or In.tructlon to
[l/Jili (Input ph ••• ).
2 1/0 port ecc ••• (TIO).
® IV dat ••• t-up tim.
(r.t.r.nced to MCLK).
•. Condition # 1
CD Progr.m .tor.g •• cc ...
tim •.
@ MCLK to LB/RS (Input
ph ••• ) or In.tructlon to
LB/RS (Input phe •• ).
® 1/0 port ecc ••• (TIO).
.1) IV del. (Input ph ••• ) to
eddr ....
b. Condition # 2
MCLK
10-115
AO-AI2
~ i I I: I
~:~
I I I I I
III~
II
I i ! I I I I I I I I
I I I I I
I I I I I I
INSTRUCTION TO: I I I
fDDRESSI • I' : : • I :
I I PROGRAM STORAGE I
ACCESS
c. Condition # 3
Figure 2-19. Constraints of 8X300 Instruction Cycle Time
F or an instruction cycle time of 250 nanoseconds and a program
storage access time of 80 nanoseconds (Condition 112), the
instruction should be valid 10 nanoseconds before the falling edge of
MCLK. This relationship can be derived by the following equation:
250 nS - TMAS - T ACC
= 250 nS - 160 nS - 80 nS
= 10 nS
It is important to note that, during the input phase, the beginning of
a valid LB/RB signal is determined by either the instruction to
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