8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

Xl
_Il_n_r
Not.
2
RESUME NORMAL
OPERATION
t
AO-A12
IV-BUS
OUTPUTS
SC&wC
i]!&1iI
MCLK
NOTES
1. A High 10 Low Iran.llion of Ih. ~ .Ignal will fore. Ih. Addr ••• Bu. 10 .n all-z.ro
configuralion.
2. Th. ~ .Ignal can .wllch from Low 10 High al any polnl within thl. tim. inl.rval and.
in all c ••••• MCLK will occur at I ... t on.-quart.r cycl. tim. lat.r ••• hown.
Figure 2-18. RESET Timing
must be done by some external means, such as an R-C network. To
ensure proper operation during normal program flow, the RESET
input must be forced low for at least one full instruction cycle.
When RESET goes low, the following takes place:
1. The Program Counter and Address Register set to zeros
asynchronously, with a delay equal to the pro~agation delay.
Their contents remain zeros as long as the RESE input remains
low.
2. The I/O bus goes to the high-impedance mode asynchronously,
and remains in this state as long as RESET is held low.
3. The SC and we outputs go low asynchronously, and remain low
as long as RESET remains low.
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