8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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A variation of this same scheme, which is suitable for use with program storage, is shown in Figure 2-23. In addition, it allows the <strong>design</strong>er to combine both bipolar and MaS ROMs within the same system. As in the previous example, a flip-flop is used to generate a hardware delay via the HALT input. <strong>Al</strong>so, the program storage has been partitioned into two equal segments - one segment composed of bipolar ROMs, the other segment composed of MaS ROMs. The state of the most significant address bit determines which program storage segment is active. Other decoding schemes can be applied to partition the memory at different ratios. 74LS109 OR EQUIVALENT AD 8X300 MCLK - K HALT r J "-e QIo- Vce 4K BYTES MaS ROM
2.4.2 I/O Interface Typical interfaces to the aX300 employ the aX32 latched addressable bidirectional I/O port. This device provides a single connection between the aX300 I/O bus and the user status and data lines. A unique feature of this I/o port is the way in which it is addressed. Each I/o port has an a-bit, field programmable address, used to enable the device. When the SC signal is high, data at the microprocessor port is treated as an address. if the address matches the I/O port's internally programmed address, the I/O port is latched into a selected state. The port remains selected until an address which does not match its internal address is presented, at which time the port is disabled. This feature eliminates the need for the additional hardware required for port enable decoding. The a-bit address field, combined with the LB/RB select bits, allow selection of one of a possible 512 I/O ports. The only disadvantage of this device is the increase in software overhead and throughput time encountered when addressing is necessary. Faster I/O selection may be implemented by adding bits to the instruction word, similar to that which was done in Figure 2-21. This technique, illustrated in Figure 2-24, allows an I/O port to be selected within the same instruction where it is used. By eliminating the need for the I/O port select instruction, important processor time is saved. The program memory extension is followed by D-type latches, and the latches in turn followed by a decoder. The outputs of the decoder, ANDed with the bank select signal, comprise the I/O port select circuitry. ME 1/0 PORT BIT N BIT 1 } EXTRA BITS ADDED FOR FAST SelECT ME 1/0 PORT BANK SelECT 16 INSTRUCTION __ --1--1 ROM 1/0 BUS 8X300 13 ADDRESS I--+---'~I Figure 2-24. Fast I/o Select For Small Systems 2-40
Page 1 and 2:
8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4: SIGNETICS ® reserves the right to
Page 5 and 6: CONTENTS Chapter Page Preface .....
Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14: 1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16: In the area of development systems,
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53: \Nhen interfacing program storage c
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106:
BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108:
BIPOLAR LSI DIVISION Command/Status
Page 109 and 110:
FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
Page 113 and 114:
BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116:
~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118:
-- u Current-Controlled Oscillator
Page 119 and 120:
2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126:
8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128:
PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
Page 131 and 132:
1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134:
BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136:
PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140:
= SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148:
APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150:
8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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