8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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- BliDD Table 1. Summary of 8X300 Instruction Set (Continued) BIPOLAR LSI DIVISION STATE OF CONTROL SIGNAL DURING INSTRUCTION CYCLE INSTRUC IIOCONT INPUT PHASE OUTPUT PHASE CLASS OPCODE FORMATS DESCRIPTION SIG (INSTRUCTION (ADDRESS & INPUT & DATA 1/0 BUS) PROCESSING) ADD 1 Same as MOVE instruction class (S) plus (AUX) - 0 Same as MOVE instruction class Same as MOVE instruction class except that contents of AUX (RO) register are ADDed to the source data. If there is a "carry" from MSB, then OVF (overflow) = 1, otherwise OVF = O. AND 2 Same as MOVE instruction class (S) /\ (AUX) - 0 Same as MOVE instruction class. Same as MOVE instruction class except that contents of AUX (RO) register are AN Oed with source data. XOR 3 Same as MOVE instruction class (S) ® (AUX) - 0 Same as MOVE instruction class. Same as MOVE instruction class except that contents of AUX (RO) register are exclusively ORed with source data. XEC 4 Execute In.tructlon at current page addre •• offset by J (literal) + (5). Return to normal In.tructlon flow unle.s a branch Is encountered. F3: Regl.ter Immediate Execute instruction at an address determined 012 1 3 4 5 6 71a 9 10 11 12 13 14 15 by replacing the low· order a·bits of the Pro· / gram Counter with the following derived sum: I OPCOOE I S J I Value of literal (J.field) plus J · Contents of internal register specified by S- Invalid values of "S": field 07 8' 17 8,2°8- 37 8 The PC is not incremented and the overflow Valid values of "J": status (OVF) is not changed. 000 8 -3778 SC = L L WC= L L IS= X X F4: 1/0 Bus Immediate Execute instruction at an address determined SC = L L 012 1 3 6 71 8 9 10 111 12 13 14 151 by replacing the low·order WC= L L 4 5 5·bits of Program Counter with the following IS= L if "S" = 208-278 X I OPCOOE I S L J derived sum: IS= H if "S" = 3°8-378 X I I I 5-bit value of literal (J-field) plus Value of rotated source data specified by Valid values of "S": 2°8-378 · S-field (The L-field specifies the length of Valid values of "J": 008-378 source data starting from the LSB-position and, if less than a·bits, the remaining bits are filled with zeros; the Program Counter is not incremented and the overflow status (OVF) is not changed.) NZT 5 If data specified by the 8-fleld Is not equal to zero, jump to current page add res. offset by value of J-fleld; otherwise, Increment the Program Counter. F3: Register Immediate If contents of internal register specified by S- 012 1 3 4 5 6 71 89 10 11 12 13 14 15 field is non-zero, transfer to address deter- / mined by replacing the low-order 8-bits of Pro- I OPCOOE I S J I I gram Counter with "J", otherwise, increment PC. Invalid values of "S": 07 8 , 178,2°8-378 Valid values of "J": 000 8 -3778 SC = L L WC= L L IS= X X F4: 1/0 Bus Immediate If right-rotated I/O bus data is non-zero, trans- SC = L L I 012 1 3 4 5 6 71 8 9 10 111 12 13 14 15/ fer to address determined by replacing low- WC = L L order 5-bits of Program Counter with "J", oth- IS= L if "S" = 20 a -27 8 X 10PCOOEl S 1 L J erwise, increment PC. (The L-field specifies IS= H if "s" = 308-37 a X 1 J the length of source 1/ 0 data starting from the LSB·position and, if less than 8-bits, the re- Valid values of "S": 208-378 maining bits are filled with zeroes.) Valid values of "J": 008-378 XMIT a F3: Regl.ter Immediate Transmit J - 0 I 1 3 71 89 15 Transmit and store 8-bit binary pattern in J- SC = L H if 0 = 078 or 178 012 4 5 6 10 11 12 13 14 1 field to internal register specified by O-field. WC = L L 10PCOOE I 0 J IS= X HifO=17 I I 8 IS= X L if 0 = 078 Invalid values of "0": 1°8,208-378 Valid values of "J": 000 8 -3778 F4: 1/0 Bus Immediate Transmit binary pattern in J-field to 1/ 0 bus. SC = L L 1 3 71 8 Before putting data on I/O bus, shift literal WC = L H 012 4 5 6 9 10 111 12 13 14 15/ value "J" as specified by thaO·field and merge IS= L if 0 = 2°8-276 L if 0 = 2°8-278 I OPCOOE I 0 L J bits specified by the L-field with existing 1/0 IS= H if 0 = 3°8-378 His 0 = 3°8-378 I I I bus data. If the L-field specifies more than 5- Valid values of "0": 2°8-378 Valid values of "J": 008-378 bits starting from the LSB'position, all remaining bits are set to zero. JMP 7 F5: Addre •• lmmedlate Jump to address in program storage specified SC = L L by A-field; this address is loaded into the Ad- WC = L L dress Register and the Program Counter. IS= X X 012 /3 4 5 6 7 8 9 10 11 12 13 14 15 I I OPCOOE· I A I Valid values of A: 00000 8 -17777 8 NOTES • RB is complement of re, X - Undefined HillnOlies 8
MIEIOEO" 11011 fR 81311 AND-data in source register or I I O-bus input is ANDed with content of AUX (RO) register and the result is placed in the destination register or I IO-bus output. Data can be shifted and I or masked, as required. XOR-data in source register or I/O-bus input is exclusively ORed with contents of AUX (RO) register and the result is placed in the destination register or I IO-bus output. Data can be shifted and I or masked, as required. XMIT -immediate data field of instruction word replaces data in destination register or I/O-bus output. XEC-executes instruction at the program address which is formed by replacing the least significant bits of the last address with the sum of: • Literal (J) field value of instruction plus, • Value of data in source register or I IO-bus input. NZT -least significant bits of program address are replaced by literal (J) field of instruction if the source register or I I O-bus is not equal to zero. JMP-program address is replaced by address field of the instruction word. Instruction Fields As shown in Table 1, each instruction contains an operations 2. BIPOLAR LSI DIVISION code (OPCODE) field and from one-to-three operand fields. The operand fields are: Source (S), Destination (D), Rotate I Length (R I L), Literal (J), and Address (A). The OPCODE and operand fields are briefly described in the following paragraphs. Operations Code Field: The three-bit OPCODE field specifies one of eight classes of 8X300 instructions; octal <strong>design</strong>ations for this field and operands for each instruction class are shown in Table 1. Source (S) and Destination (D) Fields: The five-bit (S) and (D) fields specify the source and destination of data for the operation defined by the OPCODE field. The AUXiliary (RO) register is an implied second operand for the ADD, AND, and XOR instructions, each of which require two source fields. That is, instructions of the form: ADD X, Y imply a third operand, say Z, located in the AUX (RO) register. Thus, the operation for the preceding expression is actually (X + Z), with the result stored in Y. The (S) and I or (D) fields can specify an internal 8X300 register or any oneto-eight bit I I 0 field; octal values for these registers and Source I Destination field assignments are provided in Table Table 2. Octal Addresses of 8X300 Registers and Address/Bit ASSignments of Source/Destination Fields Octal Value 8X300 Register Octal Value 8X300 Register 00 Auxiliary (RO) 10 OVF (Overflow Register)- used only as a source 01 R1 11 R11 02 R2 12 Unassigned 03 R3 13 Unassigned 04 R4 14 Unassigned 05 R5 15 Unassigned 06 R6 16 Unassigned 07 *IOL Register-Left Bank 17 *IOR Register-Right Bank I/O Address Register; I/O Address Register; Used only as destination Used only as destination NOTE ·,f IOL or lOR is specified as a source of data. the source data is all zeroes. Octal Value NOTES: 1. 2°8-278 specifies the LSB of a variable length field within the I/O port previously selected by the left·bank (lOL) register. Length of field is determined by RIL. 2. 308-378 performs the counterpart function for the right· bank register (lOR). MSB_ BYTE _ LSB 1012345671 Note 1 Note 2 20 - Field within previously selected port with LSB pOSition = 0 -------------------------. 21 - Field within previously selected port with LSB position = 1 ------------------------11 ~ 22 - Field within previously selected port with LSB position = 2 ------------......------------1- ~ 23 - Field within previously selected port with LSB position = 3 -I..... ~ 24 - Field within previously selected port with LSB position = 4 - -I .... 25 - Field within previously selected port with LSB position = 5 - - - - .... 26 - Field within previously selected port with LSB pOSition = 6 - - - - -I ..... 27 - Field within previously selected port with LSB position = 7 - - - - - ...... 30 - Field within previously selected port with LSB position = 0 _______________________--". 31 - Field within previously selected port with LSB position = 1 --------------------------' 32 - Field within previously selected port with LSB position = 2 ---------------------------' 33 - Field within previously selected port with LSB position = 3 __________________________ --1 34 -F~~wijh~pre~ou~ys~ectedportwijhLSBposmon=4 ---------------------------~ 35 -R~dwijh~pre~~~ys~ectedportwijhLSBposmon=5---------------------------~ 36 -Re~wijh~pre~ou~ys~ectedportwijhLSBposij~n=6 ------------------------------' 37 -F~~wijh~pre~ous~s~ectedportwijhLSBposmon= 7 -----------------------------~ !ifgIOliC!i 9
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79: BIPOLAR LSI DIVISION phase. During
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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