8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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SAVELOciiC RETURN ADDRESS PROM RETURN ADDRESS DISABLE ENABLE DISABLE CLOCK RETURN--~--------------------------------4_--------~--r---~ EXECUTE---r-T--------1---------------------4_---------------. 0 0 Q 0 5 Q 7474 7474 7474 INTDIS SYNC 1 ACKN Q C Ii a MCLK --------------~--------------~----~~-4~~--~----+_----~ ~------------------------------4_----~~----~~~----+_------------~--------_+----~ INTERRUPT ______________ -1 INHIBIT INT~~~~:~ __________ ...... _________ ~ INTERRUPT ACKNOWLEDGE Figure 2-31. Interrupt Control (Handshake) PROM DISABLE RETURN ADDRESS CLOCK INTERRUPT VECTOR ENABLE ~----~--------------------------------~------~~_r--~ EXECUTE----4_-r--------+---------------------~--------------, 0 0 Q 0 Q INTERRUPT ACKNOWLEDGE 7474 7474 74S74 INTDIS SYNC 1 SYNC 2 Q R C R a MCLK----------------e-------------~------r_+_4_----_r----_r------~ RESET-------------------------------4~----~~~----~----~------------~ ~--------------------_i ""iNHiBiT 7474 INTFF o t +5V INTERRUPT SIGNAL R~----------------------------------------------~ Figure 2-32. Interrupt Control (<strong>Edge</strong> And Strobe) 2-51
2.5.2 Interrupt Control (Handshake) The timing of the handshake procedure is shown in Figure 2-33. The time between the activation of the INTERRUPT signal and the leading edge of -INTERRUPT ACKNOWLEDGE (time A) is T cycle + 10 nanoseconds minimum, and 3 x tc cle + 60 nanoseconds maximum, (when Execute has to be taken inro account). The time between the de-activation of the INTERRUPT signal and the trailing edge of INTERRUPT ACKNOWLEDGE (time B) is 10 nanoseconds mimimum, and 3/4 x tcycle + 50 nanoseconds maximum. INTERRUPT SIGNAL INTERRUPT ACKNOWLEDGE Figure 2-33. Handshake Timing The INTERRUPT signal must remain active until the INTERUPT ACKNOWLEDGE goes high. The INTERRUPT ACKNOWLEDGE is de-activated when the INTERRUPT signal is no longer active. \Nhen an INTERRUPT signal occurs with no INTERRUPT INHIBIT present, the signal is synchronized in flip-flops SYNC 1 and SYNC2 because the output of SYNC1 may be a very small pulse if the INTERRUPT signal occurs very near the leading edge of MCLK. If there is an EXECUTE instruction, the setting of SYNC2 is inhibited for one cycle. When SYNC2 is set, the signals PROM DISABLE, RETURN ADDRESS CLOCK and INTERRUPT VECTOR ENABLE become active. The acknowledge flip-flop (ACKN) is also set. 2-52
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8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
Page 5 and 6:
CONTENTS Chapter Page Preface .....
Page 7 and 8:
LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16: In the area of development systems,
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65: ~LK------------------------~ +S~ 1
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
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-- u Current-Controlled Oscillator
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2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
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PRODUCT DESCRIPTION Both the 8T31 a
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8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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