8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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I ---------.~----------~ I LOW-PASS i r----------------------------------------------------------------~I FILTER I I~~I r--1~--' I CURRENT CONTROLLED L OSCILLATOR (CCO) I--------~ I I I COUNTER #1 (FEEDBACK) BIPOLAR LSI DIVISION r--~Dr--, I I CRYSTAL OSCILLATOR WRITE ..--0 READ C~:~~ ~- I r-'----....... LOAD COUNTER #2 (REFERENCE) CARRY 1 CARRY 2 '-.,r---+--I PHASE DETECTOR PUMP-UP PUMP-DOWN DATA FLIP-FLOPS (PULSE SYNCHRONIZER) t CLOCK NOTE Components shown with dashed lines are located off-chip CLOCK/DATA SEPARATION LOGIC t DATA/CLOCK WINDOWS Figure 4. Simplified Block of Phase-Lock Loop DATA ~ i ~ 4 Z ~ 3 MAXIMUM PHASE DEVIATION / FOR BOTH DATA AND CLOCK MAXIMUM PHASE DEVIATION FOR DATA 3.5 2.5 1.5 PHASE DEVIATION -+---r--;---+-~~~---1r.5--2~.S---3+.S--4~.rS---~::~~~~~ROM (LATE) MAXIMUM PHASE DEVIATION FOR BOTH DATA AND CLOCK (EARLY) NOMINAL DATA PHASE DEVIATION 4-----4+.S---3r.S--2~.S---+--~;-+---1.rS--2~.S---3+S--4~~--.~::~~~~~ROM NOMINAL DATA (LATE) 1 ~ (EARLY) MAXIMUM PHASE DEVIATION FOR DATA 2 ~ C 3~ iii 41 o c sri. :Ii ;:) II. NOTE <strong>Al</strong>l horizontal/vertical units are specified in ceo clock periods; for Standard Floppy FM Format, one ceo clock period equals 250 nanoseconds NOTE <strong>Al</strong>l horizontallvertical units are specified in ceo clock periods; for standard floppy double density (MFM/M2FM), one ceo clock period equals 125 nanoseconds Figure 5. Phase Detector Characteristic for Single-Density (FM) Format Figure 6. Phase Detector Characteristic for Double-Density (MFM/M2FM) Format 10 !ii!lDOliC!i
BIPOLAR LSI DIVISION Data Processing and Error-Check Functions These functions of the 8X330 are summarized in Figures 7 and 8. The read/write operations are software-controlled by previously-described bits of command/status registers CSR1 and CSR2. For the sake of simplicity, control lines and much of the control logic associated with the data processing and error-check functions are omitted in the read/write diagrams. CRC GENERATOR CRC ENABLE ENCODE ENABLE PRECOMP ENABLE/DISABLE WRITE GATE ENABLE CI) ;:) m g DATA REGISTER DATA SHIFT REGISTER MULTIPLEXER CLOCK ENCODING LOGIC PRECOMPENSATION LOGIC r--_L.-_ WRITE TO DISK Figure 7. Simplified Block of Data Processing and Error Check Functions-Write Mode r"'-' L CRC GENERATOR ENA[LE BYTE SYNC ENABLE - l+- i CI) DATA DATA SHIFT if- r-- MULTIPLEXER REGISTER REGISTER g CLOCK/DATA SEPARATION I LOGIC ~ CRC ------------------------------- PULSE SYNC CIRCUITS ~ READ FROM DISK "'"' PHASE LOCK LOOP 1 ______ --------------------------. Figure 8. Simplified Block of Data Processing and Error Check Functions-Read Mode !ijgDOliC!i 11
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
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Xl _Il_n_r Not. 2 RESUME NORMAL OPE
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Normally, the instruction cycle tim
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LB/RB del~ (TIIBS) or the delay tim
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Table 2-4. Bit Manipulation Functio
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The following sections provide gene
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6.154 MHz CLOCK NOMINAL r-----....
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\Nhen interfacing program storage c
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2.4.2 I/O Interface Typical interfa
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The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109: FLOP" DISI FOR.III EN/CONTROl I FR
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146: DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148: APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150: 8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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