8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

~LK------------------------~
+S~
1
P
10 --------1
::=t~
AO
A1
A2
A3
A4 -
_____ _
A
B
74123 VCC
REXT!CEXT
Q
I
I
0 C
7474
EXECUTEFF
a
SKU
,
EXECUTE
AS
A6
RETURN
A7 -----­
AS
A9
A10
A11
A12
Figure 2-30. Execute and Return Decoding
The instruction is decoded and clocked into a flip-flop about 50
nanoseconds after the trailing edge of MCLK. The output of the
flip-flop is used to stop the interrupt (see Figures 2-31 and 2-32).
To save some hardware, it is also possible to inhibit the interrupt by
means of software. In that case the hardware decoding and clocking
is not required, but before each EXECUTE instruction, one has to
make sure that the INTERRUPT INHIBIT signal is active.
At the end of the interrupt routine, an instruction, 717777, has to be
given to indicate a return. The address 17777 is on the address bus
and is decoded to form the RETURN signal. If 4K or less of
program memory is used, the decode logic (13-input gate) is no
longer necessary since the MSB(AO) alone may be used to signal a
return, that is, a jump to any address 4096.
2-50