8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

01S2 01S4 8T97 0152 0154 8T97
INTERRUPT
~~--~+-+-+-~~~~----+-+-~~~----~
ENABLE
OUT
10 11 12 13 14 15 16 17 18 19 110 111 112 113 114 115
Figure 2-36. Interrupt Vector Logic
At the start of an interrupt, the RETURN ADDRESS CLOCK loads
the Return Address Register with the current address, and the
INTERRUPT V ECTOR ENABLE forces a jump to the interrupt
address on the instruction bus.
At the return, RETURN ADDRESS ENABLE forces a jump to the
original address on the instruction bus.
2.5.5 I V L, I V R Storage Logic
The I V L and I V R storage logic is illustrated in Figure 2-37. With a
256 byte RAM (eight 82S116's), an 8X31 8-bit latched bidirectional
I/O port may be used as address latches. When a right I/O select
occurs, the I/O address is latched in the 8X31, and in a following
instruction data can be transferred in or out of the RAM.
With the interrupt circuitry, the 8X31 retains its function as
RAM-address latches, but with an I/o select instruction (SC active)
the output is disabled and the 8T97 three-state buffers force the
address 255 or 254 on the RAM address bus. If the SA V E LOGIC
DISABLE is not active, the I/O address on the data bus is written
into the RAM at address 255 Cleft IV) or 254 (right IV) by means of
the Write Enable input (WE). If SA VE LOGIC DISABLE is active,
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