8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

LB/RB del~ (TIIBS) or the delay time from the falling edge of
MCLK to LB/RB (TMIBS). Assuming the instruction is valid 10
nanoseconds before the falling edge of MCLK and adding the
instruction-to-LB/RB delay (TUBS = 35 nS), the LB/RB signal will be
valid 25 nanoseconds after the falling edge of MCLK. With a fast
program-storage memory and with a valid instruction more than 10
nanoseconds before the falling edge of MCLK -- the LB/RB signal
will; due to the T!\l1I85 delay, still be valid 25 nanoseconds after the
falling edge of MCLK. Using a worst-case instruction cycle time of
250 nanoseconds, the user cannot gain a speed advantage by
selecting a memory with faster access time. Under the same
conditions, a speed advantage cannot be obtained by using an I/O
port with fast output enable time (TID) because the address bus will
be stable 80 nanoseconds (T AS) after the beginning of the third
quarter-cycle -- no matter how early the I V data input is valid.
When operating at slower instruction cycle times (TPC > 250 nS),
there are two more timing conditions which must be satisfied in
addition to those already mentioned. First, the I/o input data must
be stable by the set-up time required by the input latches. The
program storage access time (T ACC) must be such that
T AS + T ACC + TUBS + TIC + TIDS ~
TPC
Second, the instruction must be stable by the set-up time required
by the instruction latches. The program storage access time must
also be such that
TAS + TACC + TIS ~
TPC - T2Q
where T 2Q is the length of the second quarter-cycle (pulse width
of Xl high); for symetric clock signals
T2Q = ! TPC, or
TAS + TACC + TIS ~ .75 TPC
Program storage access time must satisfy the worst case of all of
the timing conditions mentioned.
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