8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

2.3 THE 8X300 INSTRUCTION SET
The 8X300 instruction set comprises eight categories of instruction,
each identified by a di fferent OP code value. A variable operand
field within these instructions provide the equivalent of 32
instructions. During the process of an instruction, the data may
undergo some combinations of rotate, mask, and shift and merge
manipulations. Table 2-4 describes the functions that can be
performed on the data during the instruction operations. Certain
instruction operations perform no function on the data, therefore,
they do not appear in this Table (example: XMIT, Register).
The following paragraphs, in conjunction with Table 2.4, provide a
brief description of the operations that may be performed by each
of the instruction categories. It is suggested that when reading
these descriptions, the reader should also refer back to the internal
block diagram, Figure 2-11.
Op Code 0 (MO V E): Data from the source register or I/O bus is
moved to the destination register or I/O bus. Bit
manipulations may be performed as specified in Table
2-4. The source data field remains unchanged after the
operation.
Op Code 1 (ADD): Data from the source register or I/O bus is
added to the contents of the AUX register
(Accumulator). The result is then placed in the
destination register or I/O bus. Bit manipulations may be
performed as specified in Table 2-4. The source data
field and AUX register remain unchanged unless one of
those is also the destination. Only during the ADD
instruction is the value of Register 10 set. (RIO cannot
be specified as a destination.) The high order seven bits
always remain zero. The LSB is set to indicate the
carry-out of the MSB of the ALU.
NOTE: This does not indicate an overflow condition
resulting from excessive magnitude of a two's complement
sum.
Op Code 2 (AND): Data from the source register or I/O bus is
ANDed with the contents of the AUX register
(Accumulator). The result is then placed in the
destination register or I/O bus. Bit manipulations may be
performed as specified in Table 2-4. The source data
field and AUX register remain unchanged unless one of
those is also the destination.
2-31