8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

The positive edge of the INTERRUPT signal triggers the interrupt
flip-flop (INTFF). Then the synchronizaion is accomplished in the
same way as in the handshake procedure. INTERRUPT
ACKNOWLEDGE is derived from the SYNC2 output.
2.5.4 Return Address Register And Interrupt Vector
The Return Address Register is built up of four 8TIO three-state
quad D-type flip-flops. Refer to Figure 2-35. The inputs are
connected to the address bus, but the three most significant bits are
tied to "1", providing a JMP opcode (Ill) at the outputs, which are
connected to the instruction bus.
RETURN A OORESS
CLOCK
+5V
AO A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
~ I I I I I I I 1 L
8T10 8T10 8T10 I I I
L L" L
02 03
l~"
03 00 ., 02 03
00 "
CLOCK OUTOIS1 f--- CLOCK OUTOIS1 ~ CLOCK OUTOIS1 ~ CLOCK OUTOIS1 I---
-
~
"
02 03
L
".,
02
INOIS1 OUTOIS2 .-- ,...-- INOIS1 OUTDIS2 ~ .-- INOIS1 OUTOIS2 r-- r-- INOIS1 OUTOIS2 I--
INOIS2 CLEAR I-----< ~ INOIS2 CLEAR ~ ~ INOIS2 CLEAR ~---< ~ INOIS2 CLEAR I--
RETURN AD DRESS
-E-
NABLE
OV
00 01 02 03 00 01 02 03 00 01 02 03 00 01 02 03
10 11 12 13 14 15 16 17 18 19 110 111 112 113 114 115
Figure 2-35. Return Address Register
The Interrupt Vector consists of 8T97 tri-state buffers. Refer to
Figure 2-36. The inputs may be chosen to be a or 1 by means of
straps, jumpers, or switches to form the start address of the
interrupt routine. The three most significant bits, however, must be
"1" to provide a JMP opcode.
In the case of eight levels of interrupt priority, the three least
significant bits form the interrupt code.
2-54