8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

1
goes low (and remains low) during ~ first quarter-cycie, the
current instruction cycle becomes a HALT cycle. A HAL cycle
ceases the internal operation of the 8X300, but does not inhibit
MCLK or affect any internal registers. During the 'RACT cycle the
I/O bus is in a high-impedance mode, SC and WC are low, and the
address bus, AO-A12, retains the address latched in it at the time
the HALT was applied. Normal operation resumes with the cycle in
which the HALf signal is high when sampled. Refer to Figure 2-17.
,- HALT CYCLE _I
I
I
1
x,
_I I..--THH
1 I
Not. 1 THS_I 1- 1 Not. 2
=:-:r-:-:r:-:r:-::r:-:r:-::r-::r::r::rr~r~r;::r:=-:r:-::,~--------
\\\\\\.\\\"\\\\', "//////////1111/
HALT ------~~,""\::::;:-'\:::::;,:::::;""\-::,:::"~""\~,~,~,~,~,::::;,:::::" i ir-
\\\\\\\\\\\\\\\\\ /1 /1/11/11////1//
'-~'-'-'-'-'-'-'--'-'--'-'-'-\....fI-'---I t'-' JJ-/JJ~.../JJJJJJ
TMHs-1
TMHH-l
1 I
I-I
I
1-
OU~~~~~_--J~D(~-----'-J: )0~~Z~~,----__
SC&WC-_______ \ / :\ /
1
I
1
~&~ ______ ~)(~ ____ ~)(L ____ ~:~~----~)(L-----
I
MCLK
NOTES
1. The HALT signal can switch from High to Low at any time during this interval. TI+i-hold time from XI to HALl (independent of instruction cycle time)
2. The HALT signal can switch from Low to High at any time during this interval.
Timing Descriptions:
THS-set-up time Irom HALT to XI (independent of instruction cycle time)
TMHS-set-up time from MCLK to HALl (dependent upon instruction cycle time)
TMI+i-hold time from MCLK to HALl (dependent upon instruction cycle time)
Figure 2-17 • HALT Timing
Although RESET timing is not shown in Figure 2-12, it is appropriate
that it be described in this portion of text. Figure 2-18 depicts the
relationship of RESET to other signals of the 8X300.
When power is first applied to the 8X300, the RESET input of the
device must be forced low as part of the initialization process. This
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