8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

Op Code 5 (NZT): The least significant bits of the program
counter are replaced by the J field data if the register or
I/O bus specified by the source field has non-zero
contents. * Bit manipulations may be performed on I/O
destination data only as specified in Table 2-4. The
tested data field remains unchanged.
Op Code 6 (XMIT): The data in the J field is placed in the register
or I/o port specified as the destination field.* Bit
manipulations may be performed as specified in Table 2-4.
Op Code 7 (JMP): The address of the next instruction to be
executed is changed to that specified by the 13-bit A field
of the instruction.
*NOTE:
If the source field specified a register, the J field
contains an eight-bit value. If the source field speci fies
an I/O port (or memory), the J field contains a five-bit
value.
A compendium of information on instruction formats is contained in
Appendix B.
2.4 INTERFACE PRINCIPLES
Designing hardware to interface with the 8X300 Microcontroller is
primarily a task of selecting external devices that suit the job to be
done. Careful consideration must be given to the mInImum
requirements necessary to accomplish the job. Such requirements
might include instruction cycle time, memory size and memory
access time. Must the system operate with a 250 nS instruction
cycle time, or is 500 nS sufficient? At longer instruction cycle
times, slower and less expensive memory may be used. How much
External Working Storage is necessary? As External Working Storage
increases, the methods of manipulating it become more complex.
Which is the most economical method of manipulating larger and/or
slower memory - hardware or software?
Signetics offers a broad line of devices that are either specifically
designed for use with or are compatible with the 8X300. Table 2-5
provides a listing of these devices, by function. Selection of devices
from this list can greatly reduce the time and tasks necessary in
8X300 system design.
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