8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

BUS IN I EkEICE lEGIS I EI IkklY
PRELIMINARY
ARCHITECTURAL OVERVIEW
The Signetics aX320 Bus Interface Register Array (Figure 1)
is a dual-port RAM memory designed for use betwen a host
processor and a peripheral processor. SpeCifically, the register
array provides a convenient and economical interface
between the aX300 Microcontroller (secondary port) and
User's Host System (primary port); the host can be almost
any bus-oriented device-another processor, a minicomputer,
or a mainframe computer. The host has a-bit
(byte) or 16-bit (word) access to the primary port; data can
be read-from or written-into any memory location as determined
by the primary-port address and control lines. The
secondary port (aX300 bus) consists of eight input / output
lines and four bus control lines. To implement the secondaryport
interface, an a-bit memory location is addressed during
one machine cycle and, during another cycle, data is read or
written under control of the secondary (aX300) processor.
Both primary and secondary ports feature three-state out-
SECONDARY PORT
~
puts and both ports are bidirectional.
81321
BIPOLAR LSI DIVISION
Besides the convenience and economy of a two-port memory,
the array also provides simple handshake control via
two a-bit flag registers, logic to facilitate DMA transfers, and
a write-protect feature for the primary port in both byte and
word modes of operation.
FEATURES
• 16-Byte/2-Port interface
• a or 16 Bit primary-port (Host) Interface (user
selectable)
• a-Bit secondary-port Interface
• Two a-Bit flag registers (handshake control)
• DMA or programmed 1/0 operation
• Two Three-State Bidirectional Ports
• Secondary Port is bus compatible with aX300
• Single 5V supply
• 4o-Pln package
PRIMARY PORT
~
8X300
PORT LOGIC
16 X 8 MEMORY
i FLAG -REGISTER- - - -l
I PRIMARY ADDRESS: •
: ~~:D-: O~ote I
~ :~C~~D!~Y_A~~~S=:"'6~8_J
I BYTE- 28
I WORD- NOTE
~~~N~A~"--A~D~E~:~2~ _:
:GEN-PURPOSE REGISTERI
I.PRIMARY ADDRESS:
• : PRIMARY ADDRESS: I
BYTE- 48
I BYTE- 58
I
• WORD - NOTE •
~E~O~A~Y ~DDRE~:~4~ ~
i -FLAG-REGISTER- - - -
I PRIMARY ADDRESS: I
• BYTE- 18 I
I WORD - NOTE I
L _S=C:0~~':Y ~~~E~S..:. 6~8_J
r GiN -PURP-OSE REGisiER";
IGEN PURPOS"E-REGISTER:
'PRIMARY ADDRESS:
I • PRIMARY ADDRESS:
• BYTE- 38 I
I WORD _ NOTE I
~E':'O~A~Y~D~R~S~3~ J
~EN PURPOSE REGisTER:
• WORD - NOTE •
~E':'O~A~Y ~D~E~: ~8 _ J
i
I
USER-PORT
ADDRESS DECODE
USER-PORT
LOGIC
DMAE
WS
R/W
PiOE
A3
J--I---t .... _
ADDRESS LATCHES
AND
DECODE LOGIC
8X300,
DRIVERS/RECEIVERS
8
iGEN pURPoSE REGISTER:
IPRIMARY ADDRESS:
I
• BYTE- 68
I
I WORD - NOTE I
~E':O~D~R~ A~D~E~: ~6~ J
,--------- -,
.GEN PURPOSE REGISTER I
IPRIMARY ADDRESS:
I
• BYTE- 108
•
I WORD - NOTE •
~E~O~~Y ~D~R~~ ~8_ J
;GEN PURPOSE REGISTER:
IPRIMARY ADDRESS:
iGEN-PURPOSE REGISTE~
'PRIMARY ADDRESS:
•
I BYTE-148
•
I WORD - NOTE I
~E':~~~ ~D~R:S~: ~4~ _ J
iGEN-pURPoSE -REGiSTE~
IPRIMARY ADDRESS:
• I PRIMARY ADDRESS:
I BYTE-168
•
I WORD - NOTE I
~~~-:A':Y !D~':E~S:'?~8 _ J
:c3iN PURPOSE REGISTER]
I PRIMARY ADDRESS:
I
• BYTE- 78 I
• WORD - NOTE •
~E':~~R~ ~D~E~: ~7~ J
,---------.,
IGEN PURPOSE REGISTER I
I PRIMARY ADDRESS:
I BYTE- 118
I WORD - NOTE I
~E":O~D~R~ A~D.!!.E~S.:_?~ _ J
~EN~URPOSE REGISTER1
I PRIMARY ADDRESS:
I
I BYTE- 128
I BYTE-138 •
I WORD- NOTE
I WORD- NOTE
ISECONDARY L __________ ADDRESS: 728 .....J I I L SECONDARY ___________ ADDRESS: 738 ...J
IGEN -PURPOSE REGiSTER-;
: PRIMARY ADDRESS: •
I BYTE-158 I
I WORD - NOTE I
~~~N~A~Y ~D~R~S~: ~5~ J
r-------------...,
I GEN PURPOSE REGISTER I
I BYTE- 178 I
I WORD - NOTE I
~E~C:N~A~Y !-:O':E~S:_?~ _ J
NOTE:
In The Word Mode. The Registers
Are Addressed In Specific Pairs-Byte O/Byte 1. Byte 2/Byte 3.
Byte 4/Byte 5 •... Byte 14/Byte 15. And Byte 16/Byte 17
I
A2
Al
AO
B/W
D7A
D6A
D5A
D4A
D3A
D2A
D1A
DOA
D7B
D6B
D5B
D4B
D3B
D2B
D1B
DOS
Figure 1.
Block Diagram of 8X320 Bua Interface Reglater Array
!ii!lDOliCS 3