8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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R0 R0 W0 W0 1 2 1 2 X1------------~r_------_, INSTR~~T::-;IO:N:--------~L-----.J REGISTER .. MCLK (5) WORK STOR CTRL INSTRUCTION INPUT 10-115 R/L (3) (3) (2) . ROTATE CRTL LENGTH CTRL 1/0 CTRL WII2 o t RG1 (8) ALU CTRL (8) •••••••••••••••• ACCUMULATOR .---- W02 N I ........ -......J LENGTH CTRL ROTATE CTRL RII SOURCE (8) RCVR LATCHES ROTATE CTRL Re MUX W02 ... IVO-IV7 USER I/O (8) DESTINATION ROTATE CTRL Figure 2-11. 8X300 Detailed Block Diagram
XI ~~---------------------------------TPC------------------.I r=TCL~_TCP~ --------~l~------~ I I 1 MCLK : I~~~------~--------------~I 1 ~I --------- ! I. ~ITW~ ADDRESS ---------------I~------------~------------~--------\"~~~r----------------------------------- (AO-AI2) INSTRUCTION (10-115) SClWC I..------------------.!...-----TIA ------+-1....------ I. TIVA-----Io-l I+----------TIH ~-----__I~ ~------------...:...--TMIH~---__I~ I 1 I I 1 : ~ I ~ TIBS rt--___ _______ TMWH----.!.-t----T-W-H-.-J I I • I II ~I~ ______________________ ~----JII~----------~~------------JI'~--------------------~---' HALT ------------------~~~--~ ~ INDICATES CHANGING DATA Em INDICATES 3·STATE NOTE For an instruction cycle time greater than 250 ns. the 1/0 bus can be stable sometime within the third quarter (T 30) cycle. TIIB'S~ . ~TIO---..I.TIDS~ :. TOBS_ '--- 1 ~TMIDS--l I ~ : TMOBS 1- TODH_ -I TMODH - It''' I TMIDH I TIDH I I. TDD~ ,j 1 OUTPUT INPUT OUTPUT TMHS ~ Ij 1 ~~ 1 1 t:=TMHH I .. TODS TMODS :..- INPUT PHASE (R;) -..:.- OUTPUT PHASE (W;) -.j I . 1 ~ In.l.uction •• g ----.: l..-ln.l.uclion .dd .... ~MCLK hi h---...l 1 open I 1 ch.ng.. 1 g I : : 1 sc = "1~ 10. I/O : I", SC = WC = "0" ~ 1 .. odd ..... WC = "1"10' .1 : ! : I/O~m. : I" LA. M •• 1 ',0' Inpul dm. • :.. LA.M •• t I~. oulput dm. ~ : : r-- odd .... 10 110 BUS; ~h""'lm. olh •• wl.. I : ! I ! : I" I/O d.lv ... Ih ... ·.I.I. • 1 I/O d.lv ... actlv. II oulpul dm. o. ~ :.. I/O .ec.I;V ... open • : : i : I I 1 14--~I/Obu"l.bI.~ 1 : 1 NoTE1 1 :...-- R~1 ---'~R~2 ---.:.--- W~1 ---":"-W~2 -+l I,.. I ONE CYCLE ( ·250 n5) I .1 I I I I I :1 TMWL Figure 2-12. 8X300 Instruction Cycle Timing 2-18
Page 1 and 2: 8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4: SIGNETICS ® reserves the right to
Page 5 and 6: CONTENTS Chapter Page Preface .....
Page 7 and 8: LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10: FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12: 1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14: 1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16: In the area of development systems,
Page 17 and 18: MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31: 2.2 8X300 TIMING To understand the
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84:
MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86:
BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88:
111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90:
: ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92:
BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94:
UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96:
BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98:
81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100:
BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102:
PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104:
BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106:
BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108:
BIPOLAR LSI DIVISION Command/Status
Page 109 and 110:
FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112:
BIPOLAR LSI DIVISION Data Processin
Page 113 and 114:
BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116:
~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118:
-- u Current-Controlled Oscillator
Page 119 and 120:
2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122:
2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124:
PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126:
8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128:
PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130:
113271]33/1135/1136 1I12jll16 1142
Page 131 and 132:
1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134:
BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136:
PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138:
PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140:
= SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144:
PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146:
DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148:
APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150:
8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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