8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

More documents

Recommendations

Info

'110'_ [II' System determinants for the instruction cycle time are: • Propagation delays within the 8X300 • Access time of Program Storage • Enable time of the I I 0 port Normally, the instruction cycle time is constrained by one or more of the following conditions; Condition 1-lnstruction or MCLK to LB I RB (input phase) plus I I 0 port access time (TIO) ~ IV data setup time (Figure 4a). Condition 2-Program storage access time (TACC) plus instruction to LB IRS (input phase) plus I I 0 port access time (TIO) plus IV data (input phase) to address ~ instruction time (Figure 4b). Condition 3-Program storage access time plus instruction to address ~ instruction cycle time (Figure 4c). MCLK ~: SC,WC,[!orfil! ~i I I MCLK I 1-1 \ill t- : 1-=: I II I I-@-ti : I I I a. CondHlon # 1 I I I: I: I AO-A12~ I! mr= ! I I I I :(1 MCLK to [!/fiI! (Input pha.e) Or In.tructlon to : [!/fiI! (Input pha ..). 1:2~ liD port ecce •• (TID). I @ IV data .et-up time i (referenced to MCLK). I I ~~J I I " I I I iGl---~ time. 10-115 :: I I: I® MCLK to LB/RS (Input I I M:t : :- I_~r I ® : I I ph ... ) or Instruction to I I LB/RB (Input ph •• e). I I I I I I@ liD por1 ecce •• (TID). LB, J!m: I I ~ r.-: _! 10 IV data (Input pha.e) to iVij_jV7: I I : MCLK 10-115 A()'A12 Figure 4. b. Condition # 2 ! II i :~ ~i':: : : : !:: I I I I I I I I I I I INSTRUCTION TO I I I I I ADDRESS I I I I I I I 'I I 1'1 I I I PROGRAM STORAGE I ACCESS c. Condition #3 Constraints of 8X300 Instruction Cycle Time 8] JDD BIPOLAR LSI DIVISION From condition # 1 and with an instruction cycle time of 250 ns, the I I 0 port access time (TIO) can be calculated as follows: TMIBS + TIO ~ TMIDS transposing, TIO ~ TMIDS - TMIBS substituting, TIO ~ 55ns - 25ns result, TIO ~ 30 ns Using 30 ns for TIO, the constraint imposed by condition # 1 can also be used to calculate the minimum cycle time: TMIBS + TIO ~ TMIDS thus, 25ns + 30ns ~ T 10 + T20 - 70 25ns + 30ns ~ % cycle - 70 therefore, the worst-case instruction cycle time is 250 ns. With subject parameters referenced to X 1, the same calculations are valid: TIBS + TIO + TIDS ~ % cycle thus, 70ns + 30ns + 25ns ~ % cycle therefore, the worst-case instruction cycle time is again 250 ns. From condition # 2 and with an instruction cycle time of 250 ns, the program storage access time can be calculated: TACC + TIIBS + TIO + TIVA ~ 250ns transposing, TACC ~ 250ns - TIIBS - TIO -TIVA substituting, TACC ~ 250ns - 35ns - 30ns -105ns thus, TACC ~ 80ns hence, for an instruction cycle time of 250 ns, a program storage access time of 80 ns is implied. The constraint imposed by condition #3 can be used to verify the maximum program storage access time: TIA + TACC ~ Instruction Cycle thus, TACC ~ 250ns - 170ns and, TACC ~ 80ns, confirming that a program storage access time of 80 ns is satisfactory. For an instruction cycle time of 250 ns and a program storage access time of 80 ns (Condition #2/Figure 4b), the instruction should be valid 10 ns before the falling edge of MCLK. This relationship can be derived by the following equation: 250ns - TMAS - TACC = 250ns - 160ns - 80ns 10ns It is important to note that, during the input phase, the beginning of a valid LB/RB signal is determined by either the instruction to LB I RB delay (TIIBS) or the delay from the falling edge of MCLK to LB I RB (TMIBS). Assuming the instruction is valid 10 ns before the falling edge of MCLK and adding the instruction-to-LB I RB delay (TIIBS) = 30ns), the LB I RB signal will be valid 25 ns after the falling edge of MCLK. With a fast program storage memory and with a valid instruction more than 10 ns before the falling edge of MCLK-the LB/RB signal will, due to the TMIBS delay, still be valid 25 ns after the falling edge of MCLK. Using a worstcase instruction cycle time of 250 ns, the user cannot gain a speed advantage by selecting a memory with faster access time. Under the same conditions, a speed advantage cannot be obtained by using an I I 0 port with fast access time (TIO) because the address bus will be stable 80 ns (TAS) after the beginning of the third quarter cycle-no matter how early the IV data input is valid. 18 9i!1111iC9
BIPOLAR LSI DIVISION Internal Timing and Timing Relationships <strong>Al</strong>l timing and timing-control signals of the 8X300 are generated by the oscillator and sequencer shown in Figure 5. The sequencer outputs direct and control all of the timing parameters specified in the TIMING DIAGRAM. Observe that each input quarter cycle bears a fixed relationship to X 1 via the propagation delay. General and interactive timing relationships pertaining to I/O signals of the 8X300 are shown in Figure 6. Example-in the input phase, the switching point of the LB / RB signal is caused by the worst-case delay from the instruction to LB / RB or from the beginning of the first internal quarter cycle to LB / RB; the two arrows pointing to the LB / RB transition indicate this "either / or" dependency. This information coupled with tabular values and the TIMING DIAGRAM provides the user with the wherewithal to calculate any and all system timing parameters. CLOCK CONSIDERATIONS The on-chip os'cillator and timing-generation circuits of the 8X300 can be controlled by anyone of the following methods: Capacitor: if timing is not critical Crystal: if preCise timing is required External Drive: if application requires that the 8X300 be synchronized with system clock Capacitor Timing: A non-polarized ceramic or mica capacitor with a working voltage equal to or greater than 25-volts is recommended. The lead lengths of capacitor should be approximately' the same and as short as possible; also, the Xl X2 OSCILLATOR ,----- MCLK SEQUENCER FIRST QUARTER-CYCLE SECOND QUARTER-CYCLE THIRD QUARTER-CYCLE '-----= FOURTH QUARTER-CYCLE '---------='" ") L L L L ~Y~: -I FIRST 1 SECOND 1 THIRD 1 FOURTH 1 QUARTER-CYCLE QUARTER-CYCLE QUARTER-CYCLE QUARTER-CYCLE 1 = 1 ~ ,I Figure 5. Timing and Timing Control Signals of the 8X300 timing circuits should not be in close proximity to external sources of noise. For various capacitor (ex) values, the cycle time can be approximated as: C x (in pF) APPROXIMATE CYCLE TIME 100 300 ns 200 500 ns 500 1.1 /.LS 1000 2.0/.Ls 4 QUARTE~~~~~~:; ----+-------j:11------+----~IT_::::::__---i&_----__a;f------ MCLK ADDRESS--------+----------r---+-""""'" AO-A12 "'"¥:------------- SC/WC--------+-~.." [B/RB ---------~~~ HA~ ____________--" NOTES \'-__ ~I ~ DENOTES CHANGING DATA mm DENOTES HI·Z Figure 6. Timing Relationships of 8X300 1/0 Signals !i!!lIOliCS 19
Page 1 and 2:
8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
Page 5 and 6:
CONTENTS Chapter Page Preface .....
Page 7 and 8:
LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
Page 11 and 12:
1.1 INTRODUCTION The Signetics 8X30
Page 13 and 14:
1.2 DESIGN AD V ANT AGES OF THE SIG
Page 15 and 16:
In the area of development systems,
Page 17 and 18:
MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20:
The function of the operand fields
Page 21 and 22:
The Program Address logic data flow
Page 23 and 24:
1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26:
\- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28:
OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30:
The second, and most desirable, met
Page 31 and 32:
2.2 8X300 TIMING To understand the
Page 33 and 34:
XI ~~------------------------------
Page 35 and 36:
Table 2-3. 8X300 AC Electrical Char
Page 37 and 38:
2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142:
PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144:
PRELIMINARY BIPOLAR LSI DIVISION US
Page 145 and 146:
DC ELECTRICAL CHARACTERISTICS Vee =
Page 147 and 148:
APPENDIX B INSTRUCTION FORMATS B-1
Page 149 and 150:
8X300 INSTRUCTION SET S R/L 1314151
show all

8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

Create successful ePaper yourself

Delete template?

Save as template?