8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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18 BIPOLAR LSI DIVISION VOLTAGE REGULATOR All internal logic of the 8X300 is powered by an on-chip voltage regulator that requires an external series-pass transistor. Electrical specifications for the off-chip power transistor and a typical hook-up are shown in the accompanying diagram. To minimize lead inductance, the transistor should be as close as possible to the 8X300 package and the emitter should be ac-grounded via a o. 1-microfarad ceramic capacitor. VCC PARAMETER hIe BEON BX300 VCR 1 + VCESAT "'T'" 0.1/,1 VCR BVCEO ~- It NOTE: Typical approved parts-2N5320, 2N5337 CONDITIONS LIMITS VCE = 2V; ·50 l00mA
BUS IN I EkEICE lEGIS I EI IkklY PRELIMINARY ARCHITECTURAL OVERVIEW The Signetics aX320 Bus Interface Register Array (Figure 1) is a dual-port RAM memory designed for use betwen a host processor and a peripheral processor. SpeCifically, the register array provides a convenient and economical interface between the aX300 Microcontroller (secondary port) and User's Host System (primary port); the host can be almost any bus-oriented device-another processor, a minicomputer, or a mainframe computer. The host has a-bit (byte) or 16-bit (word) access to the primary port; data can be read-from or written-into any memory location as determined by the primary-port address and control lines. The secondary port (aX300 bus) consists of eight input / output lines and four bus control lines. To implement the secondaryport interface, an a-bit memory location is addressed during one machine cycle and, during another cycle, data is read or written under control of the secondary (aX300) processor. Both primary and secondary ports feature three-state out- SECONDARY PORT ~ puts and both ports are bidirectional. 81321 BIPOLAR LSI DIVISION Besides the convenience and economy of a two-port memory, the array also provides simple handshake control via two a-bit flag registers, logic to facilitate DMA transfers, and a write-protect feature for the primary port in both byte and word modes of operation. FEATURES • 16-Byte/2-Port interface • a or 16 Bit primary-port (Host) Interface (user selectable) • a-Bit secondary-port Interface • Two a-Bit flag registers (handshake control) • DMA or programmed 1/0 operation • Two Three-State Bidirectional Ports • Secondary Port is bus compatible with aX300 • Single 5V supply • 4o-Pln package PRIMARY PORT ~ 8X300 PORT LOGIC 16 X 8 MEMORY i FLAG -REGISTER- - - -l I PRIMARY ADDRESS: • : ~~:D-: O~ote I ~ :~C~~D!~Y_A~~~S=:"'6~8_J I BYTE- 28 I WORD- NOTE ~~~N~A~"--A~D~E~:~2~ _: :GEN-PURPOSE REGISTERI I.PRIMARY ADDRESS: • : PRIMARY ADDRESS: I BYTE- 48 I BYTE- 58 I • WORD - NOTE • ~E~O~A~Y ~DDRE~:~4~ ~ i -FLAG-REGISTER- - - - I PRIMARY ADDRESS: I • BYTE- 18 I I WORD - NOTE I L _S=C:0~~':Y ~~~E~S..:. 6~8_J r GiN -PURP-OSE REGisiER"; IGEN PURPOS"E-REGISTER: 'PRIMARY ADDRESS: I • PRIMARY ADDRESS: • BYTE- 38 I I WORD _ NOTE I ~E':'O~A~Y~D~R~S~3~ J ~EN PURPOSE REGisTER: • WORD - NOTE • ~E':'O~A~Y ~D~E~: ~8 _ J i I USER-PORT ADDRESS DECODE USER-PORT LOGIC DMAE WS R/W PiOE A3 J--I---t .... _ ADDRESS LATCHES AND DECODE LOGIC 8X300, DRIVERS/RECEIVERS 8 iGEN pURPoSE REGISTER: IPRIMARY ADDRESS: I • BYTE- 68 I I WORD - NOTE I ~E':O~D~R~ A~D~E~: ~6~ J ,--------- -, .GEN PURPOSE REGISTER I IPRIMARY ADDRESS: I • BYTE- 108 • I WORD - NOTE • ~E~O~~Y ~D~R~~ ~8_ J ;GEN PURPOSE REGISTER: IPRIMARY ADDRESS: iGEN-PURPOSE REGISTE~ 'PRIMARY ADDRESS: • I BYTE-148 • I WORD - NOTE I ~E':~~~ ~D~R:S~: ~4~ _ J iGEN-pURPoSE -REGiSTE~ IPRIMARY ADDRESS: • I PRIMARY ADDRESS: I BYTE-168 • I WORD - NOTE I ~~~-:A':Y !D~':E~S:'?~8 _ J :c3iN PURPOSE REGISTER] I PRIMARY ADDRESS: I • BYTE- 78 I • WORD - NOTE • ~E':~~R~ ~D~E~: ~7~ J ,---------., IGEN PURPOSE REGISTER I I PRIMARY ADDRESS: I BYTE- 118 I WORD - NOTE I ~E":O~D~R~ A~D.!!.E~S.:_?~ _ J ~EN~URPOSE REGISTER1 I PRIMARY ADDRESS: I I BYTE- 128 I BYTE-138 • I WORD- NOTE I WORD- NOTE ISECONDARY L __________ ADDRESS: 728 .....J I I L SECONDARY ___________ ADDRESS: 738 ...J IGEN -PURPOSE REGiSTER-; : PRIMARY ADDRESS: • I BYTE-158 I I WORD - NOTE I ~~~N~A~Y ~D~R~S~: ~5~ J r-------------..., I GEN PURPOSE REGISTER I I BYTE- 178 I I WORD - NOTE I ~E~C:N~A~Y !-:O':E~S:_?~ _ J NOTE: In The Word Mode. The Registers Are Addressed In Specific Pairs-Byte O/Byte 1. Byte 2/Byte 3. Byte 4/Byte 5 •... Byte 14/Byte 15. And Byte 16/Byte 17 I A2 Al AO B/W D7A D6A D5A D4A D3A D2A D1A DOA D7B D6B D5B D4B D3B D2B D1B DOS Figure 1. Block Diagram of 8X320 Bua Interface Reglater Array !ii!lDOliCS 3
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8H500 DESIGn GUIDE Smn~liCS a subsi
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SIGNETICS ® reserves the right to
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CONTENTS Chapter Page Preface .....
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LIST OF TABLES TABLE PAGE 2-1 2-2 2
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FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
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The function of the operand fields
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The Program Address logic data flow
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1. ~elect ~ommand (SC) - a high (bi
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\- INPUT PHASE MCLK= LOW OUTPUT PHA
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OUTPUT OF ALU o I I I I I I v _L-BI
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The second, and most desirable, met
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2.2 8X300 TIMING To understand the
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XI ~~------------------------------
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Table 2-3. 8X300 AC Electrical Char
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2.2.2 Timing Calculations It is an
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INSTRUCTION •••• tI INPUT I
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Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69 and 70: The positive edge of the INTERRUPT
Page 71 and 72: the writing of I/O addresses is inh
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
Page 121 and 122: 2048 BII BIPOtAR RAM (25618) PRELIM
Page 123 and 124: PRODUCT DESCRIPTION Both the 8T31 a
Page 125 and 126: 8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
Page 127 and 128: PRODUCT IDENTITY aT32- Three-state,
Page 129 and 130: 113271]33/1135/1136 1I12jll16 1142
Page 131 and 132: 1 BII LATCHED ADDRESSABLE BIDIRECTI
Page 133 and 134: BIPOLAR LSI DIVISION ADDRESS PROGRA
Page 135 and 136: PRELIMINARY SPECIFICATION DESCRIPTI
Page 137 and 138: PRELIMINARY SPECIFICATION ABSOLUTE
Page 139 and 140: = SABEl =---=========--__ F PRELIMI
Page 141 and 142: PRELIMINARY BIPOLAR LSI DIVISION DC
Page 143 and 144: PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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