8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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01S2 01S4 8T97 0152 0154 8T97 INTERRUPT ~~--~+-+-+-~~~~----+-+-~~~----~ ENABLE OUT 10 11 12 13 14 15 16 17 18 19 110 111 112 113 114 115 Figure 2-36. Interrupt Vector Logic At the start of an interrupt, the RETURN ADDRESS CLOCK loads the Return Address Register with the current address, and the INTERRUPT V ECTOR ENABLE forces a jump to the interrupt address on the instruction bus. At the return, RETURN ADDRESS ENABLE forces a jump to the original address on the instruction bus. 2.5.5 I V L, I V R Storage Logic The I V L and I V R storage logic is illustrated in Figure 2-37. With a 256 byte RAM (eight 82S116's), an 8X31 8-bit latched bidirectional I/O port may be used as address latches. When a right I/O select occurs, the I/O address is latched in the 8X31, and in a following instruction data can be transferred in or out of the RAM. With the interrupt circuitry, the 8X31 retains its function as RAM-address latches, but with an I/o select instruction (SC active) the output is disabled and the 8T97 three-state buffers force the address 255 or 254 on the RAM address bus. If the SA V E LOGIC DISABLE is not active, the I/O address on the data bus is written into the RAM at address 255 Cleft IV) or 254 (right IV) by means of the Write Enable input (WE). If SA VE LOGIC DISABLE is active, 2-55
the writing of I/O addresses is inhibited. Only data that has to 'be written into the RAM at a specifc address will be written by means of the Write Control (we) signal, if the RB signal is active to enable the RAM by means of the CEl input. Only one of the eight RAM cells, 825116, has been drawn in Figure 2-37. RAM ADDRESS BUS BT97 OUT6 OUT5 OUT" I DIS2 IN6 f---< IN5 f---< IN" f---< OUT3 IN3 10- OUT2 IN2 10- OUT1 IN1 f---< +5V f r AO A1 A,2 A3 A" A5 A6 A7 AO A1 A2 A3 A,,, A5 A6 A7 DIS2 .------ CE1 +5V- BOC Rc I--+SV C 828116 sc- SiC BT31 wc I-- sc - CE3 _ WE I- iiii- ME ClK I--MClK " DIS4 I ~ OUT6 IN6 I-- OUTS INS I-- 01 t DO BO B1 B3B4 B6 B7 - l- - I- - I- - I- MClK SAVE lOGIC DISABLE sc we - D sc sc - ..... "'" I J - - Q>-r - "..., ." we RB Figure 2-37. I V L, I V R Storage Logic 2.5.6 Priority Interrupt Levels Figure 2-38 shows part of the logic for an eight level interrupt priority. The remainer of the interrupt control logic is depicted in Figure 2-32. (<strong>Edge</strong> and Strob~), with the exception that one interrupt flip-flop (INTFF) is replace by a number of flip-flops, INTFF A, INTFFB, etc. A handshake procedure is also possible. 2-56
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8H500 DESIGn GUIDE Smn~liCS a subsi
Page 3 and 4:
SIGNETICS ® reserves the right to
Page 5 and 6:
CONTENTS Chapter Page Preface .....
Page 7 and 8:
LIST OF TABLES TABLE PAGE 2-1 2-2 2
Page 9 and 10:
FIGURE LIST OF ILLUSTRATIONS (Cont.
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1.1 INTRODUCTION The Signetics 8X30
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1.2 DESIGN AD V ANT AGES OF THE SIG
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In the area of development systems,
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MERGE lOGIC ~IVO ~IVl _.~IV2 (Nole.
Page 19 and 20: The function of the operand fields
Page 21 and 22: The Program Address logic data flow
Page 23 and 24: 1. ~elect ~ommand (SC) - a high (bi
Page 25 and 26: \- INPUT PHASE MCLK= LOW OUTPUT PHA
Page 27 and 28: OUTPUT OF ALU o I I I I I I v _L-BI
Page 29 and 30: The second, and most desirable, met
Page 31 and 32: 2.2 8X300 TIMING To understand the
Page 33 and 34: XI ~~------------------------------
Page 35 and 36: Table 2-3. 8X300 AC Electrical Char
Page 37 and 38: 2.2.2 Timing Calculations It is an
Page 39 and 40: INSTRUCTION •••• tI INPUT I
Page 41 and 42: Xl _Il_n_r Not. 2 RESUME NORMAL OPE
Page 43 and 44: Normally, the instruction cycle tim
Page 45 and 46: LB/RB del~ (TIIBS) or the delay tim
Page 47 and 48: Table 2-4. Bit Manipulation Functio
Page 49 and 50: The following sections provide gene
Page 51 and 52: 6.154 MHz CLOCK NOMINAL r-----....
Page 53 and 54: \Nhen interfacing program storage c
Page 55 and 56: 2.4.2 I/O Interface Typical interfa
Page 57 and 58: The preceding descriptions should n
Page 59 and 60: ~ SIGNETICS 8X32 1/0 PORT - LB -- .
Page 61 and 62: stored in the successi ve-approxima
Page 63 and 64: g) Priority logic - If more than on
Page 65 and 66: ~LK------------------------~ +S~ 1
Page 67 and 68: 2.5.2 Interrupt Control (Handshake)
Page 69: The positive edge of the INTERRUPT
Page 73 and 74: The outputs of the flip-flops are u
Page 75 and 76: 10 11 12 SHIFT LOGIC MERGE LOGIC 13
Page 77 and 78: BIPOLAR LSI DIVISION PROGRAM STORAG
Page 79 and 80: BIPOLAR LSI DIVISION phase. During
Page 81 and 82: MIEIOEO" 11011 fR 81311 AND-data in
Page 83 and 84: MICRacalTRaLLER 8X311 BIPOLAR LSI D
Page 85 and 86: BIPOLAR LSI DIVISION AC CHARACTERIS
Page 87 and 88: 111£60£uNJIOLLER 11300 BIPOLAR LS
Page 89 and 90: : ... BIPOLAR LSI DIVISION 8X300 TI
Page 91 and 92: BIPOLAR LSI DIVISION Internal Timin
Page 93 and 94: UICIOGONTIOLLEI BIPOLAR LSI DIVISIO
Page 95 and 96: BUS IN I EkEICE lEGIS I EI IkklY PR
Page 97 and 98: 81320 PRELIMINARY OPERATING CHARACT
Page 99 and 100: BUS IN I EIEICE lEGIS I EI lIllY PR
Page 101 and 102: PRELIMINARY elPOLAR LSI DIVISION AC
Page 103 and 104: BIPOLAR LSI DIVISION ARCHITECTURAL
Page 105 and 106: BIPOLAR LSI DIVISION SYSTEM INTERFA
Page 107 and 108: BIPOLAR LSI DIVISION Command/Status
Page 109 and 110: FLOP" DISI FOR.III EN/CONTROl I FR
Page 111 and 112: BIPOLAR LSI DIVISION Data Processin
Page 113 and 114: BIPOLAR LSI DIVISION DC CHARACTERIS
Page 115 and 116: ~ FLOPPY DISK FORMATTER fGONTROLLER
Page 117 and 118: -- u Current-Controlled Oscillator
Page 119 and 120: 2048 BII BlrOtliliM (25618) PRELIMI
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2048 BII BIPOtAR RAM (25618) PRELIM
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PRODUCT DESCRIPTION Both the 8T31 a
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8-d" LIIEHED dlSl EEI'ONAL ./0 POIT
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PRODUCT IDENTITY aT32- Three-state,
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113271]33/1135/1136 1I12jll16 1142
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1 BII LATCHED ADDRESSABLE BIDIRECTI
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BIPOLAR LSI DIVISION ADDRESS PROGRA
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PRELIMINARY SPECIFICATION DESCRIPTI
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PRELIMINARY SPECIFICATION ABSOLUTE
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= SABEl =---=========--__ F PRELIMI
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PRELIMINARY BIPOLAR LSI DIVISION DC
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PRELIMINARY BIPOLAR LSI DIVISION US
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DC ELECTRICAL CHARACTERISTICS Vee =
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APPENDIX B INSTRUCTION FORMATS B-1
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8X300 INSTRUCTION SET S R/L 1314151
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8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

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