8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

2.5 8X300 INTERRUPT STRUCTURE
Although the 8X300 microprocessor is a very fast device and in
many cases external events occurring randomly and influencing the
program flow may be discovered by means of a polling technique,
there are instances when the system must react immediately to such
events.
Because the 8X300 has no interrupt facility, it is necessary to add
hardware to obtain such a facility. This hardware should perform
the following actions on receipt of an interrupt signal:
- save the current Program Counter contents
- retain the last used I V L and I V R addresses
- make the program jump to a fixed (interrupt) address
- detect a return instruction
- restore the I V L and I V R addresses
- restore the original contents of the Program Counter
Any registers which are used in the interrupt routine should also be
saved and restored on return; this is done in software as is the
restoration of the IVL and IVR addresses, although the saving is
done by hardware. To save and restore various items, a RAM of at
least ten bytes is required. However, it is assumed that a 256 byte
RAM is available, connected to the right bank.
To provide an interrupt facility for 8X300 systems, it is necessary to
add the following hardware:
a) EXECUTE decoding - Interrupts must be inhibited during an
EXECUTE instruction
b) Return decoding - 717777 (JMP 17777) is used as a return
instruction. The address 17777 must be decoded
c) Interrupt control - The Interrupt signal has to be synchronized
with the Master Clock, and various control signals have to be
generated
d) Return Address Register
e) Interrupt Vector logic - This logic forces a jump to the interrupt
address on the instruction bus
f) I V L, I V R Save logic - It is necessary to retain the last I V Land
I V R addresses selected before the interrupt, to be able to
restore these addresses on ret urn
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