8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

when an interrupt occurs, a signal INTERRUPT ACKNOWLEDGE is
generated. The timing depends upon whether a handshake interrupt
or an edge and stobe interrupt is chosen.
The implementation of the interrupt facility as described requires
20 OIL devices .
8X300
1/0 BUS
..- __ iiiiiil __-
r::::-l=
..... IL.::..F
~~------------------~~
ADDRESS
INSTRUCTION
EXECUTE
RETURN ADDRESS ENABLE
RETURN ADDRESS CLOCK
ADDRESS 17777
SAVE LOGIC
DISABLE
IVL.IVR
SAVE
LOGIC
PROM
PROM
DISABLE
INTERRUPT
CONTROL
INTERRUPT INHIBIT
..-----INTERRUPT SIGNAL
t-----~ INTERRUPT ACKNOWLEDGE
Figure 2-29. Typical Interrupt Block Diagram
2.5.1 Execute and Return Decoding
The EXECUTE and RETURN decoding logic is shown in Figure 2-30.
When an EXECUTE instruction (opcode 100) is encountered, the
content of the address bus is not equal to that of the Program
Counter. At that moment no interrupt may occur. To detect
whether an EXECUTE instruction is being performed, however,
requires a delay of the trailing edge of MCLK because the
instruction bus becomes valid after this trailing edge. Prior to the
leading edge of the next MCLK the address changes, causing the
instruction to also change.
2-49