8x300 design guide - Al Kossow's Bitsavers - Trailing-Edge

Normally, the instruction cycle time is constrained by one or more
of the following conditions:
Condition 1 --
Instruction or MCLK to LB/RB (input phase) plus
I/O port output enable (TID) ~ I V data set-up time
(Figure 2-19a)
Condition 2 -- Program storage access tfme (T ACC) plus
instruction to CB/RB (input phase) plus I/O port
output enable (TID) plus I V data (input phase) to
address ~ instruction cycle time (Figure 2-19b).
Condition 3 --
Program Storage access time plus instruction to
address ~ instruction cycle time (Figure 2-19c).
From condition III and with an instruction cycle time of 250
nanoseconds, the I/O port output enable time (TID) can be
calculated as follows:
transposing,
substituting,
result,
TMIBS + TID $ TMIDS
TID ~ TMIDS - TMIBS
TID ~ 55nS - 25 nS
TID ~ 30 nanoseconds
Using 30 nanoseconds for TID, the constraint imposed by Condition
III can also be used to calculate the minimum cycle time:
TMIBS + TID ~ TMIDS
thus, 25 nS + 30 nS ~ TIQ + T2Q - 70
25 nS + 30 nS ~ t cycle - 70 therefore,
the worst-case instruction cycle time is 250 nanoseconds. With
subject parameters referenced to Xl, the same calculations are
valid:
TIBS + TID + TIDS ~ t cycle
thus,
70 nS + 30 nS + 25 nS 5' ! cycle therefore,
the worst-case instruction cycle time is again 250 nanoseconds.
From Condition 112 and with an instruction cycle time of 250
nanoseconds, the program storage access time can be calculated:
TACC + TIIBS + TID + TIV AS 250 nS
transposing, TACC ~ 250 nS - TIIBS - TID - TIV A
substituting, T ACC ~ 250 nS - 35 nS - 30 nS - 105 nS
thus, T ACC ~ 80 nS hence, for an instruction cycle
time of 250 nanoseconds, a program storage access time of 80
nanoseconds is implied. The constraint imposed by Condition 113 can
be used to verify the maximum program storage access time:
2-28