24/06/2005 - Controller General of Patents, Designs, and Trade Marks

(12) PATENT APPLICATION PUBLICATION
(19) INDIA (21)
(22) Date of filing of
Application:
24/05/2004 (43)
(54) Title of the invention: VEDIC MULTIPLIER
(51) International
Classification:
G06F 7/52 (71)
(31) Priority Document No.: NIL
(32) Priority Date:
NIL
(33) Name of priority country: NIL
(86)
International Application No. & Filing Date:
NIL
NIL
(87) International Publication No.: NIL
(61)
(62)
Patent of addition to Application No.: NIL
Filed on: N.A.
Divisional to
Application No.: NIL
Filed on: N.A.
EARLY PUBLICATION
Application No: 588/MUM/2004 A
(72)
Publication Date: 24/06/2005
Name of the Applicant:
ASHTEKAR DHARMENDRA
SUDHAKAR
Address of the Applicant:
C/O S.M. SANSARE,
THRIMURTI C.H.S., 509/C-1
CHARKOP, SECTOR- 5,
KANDIVLI (W), MUMBAI 400 067.
Name of the Inventors:
ASHTEKAR DHARMENDRA
SUDHAKAR
Filed U/S 5(2) before the
Patents (Amendment)
Ordinance, 2004: NO
(57) Abstract : Two bit Vedic Multiplier circuit carries out multiplication of two binary numbers, with a time
delay of 2 logic gates. This circuit doesn’t make use of shift registers. By adopting this technique of Vedic
Multiplier for higher values of ‘n’ time taken for multiplication of two binary numbers is reduced.
(FIG. ) : NIL
Total pages : 17
The Patent Office Journal 24.06.2005 17703