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24/06/2005 - Controller General of Patents, Designs, and Trade Marks

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(21) Application No. 1022/DEL/2000 A (22) Date <strong>of</strong> filing <strong>of</strong> Application: 14/11/2000<br />

(54) Title <strong>of</strong> the invention: “ELECTRONIC PACKAGE AND METHOD OF FORMING<br />

ELECTRONIC PACKAGE.”<br />

(51) International Classification 7 :<br />

H01L 23/48, H01L23/12<br />

(30) Priority Data :<br />

(31) Document No.: 09/471,679<br />

(32) Date : 23.12.1999<br />

(33) Name <strong>of</strong> convention country : U.S.A..<br />

(66) Filed U/s 5(2) : NIL<br />

(61) Patent <strong>of</strong> addition to application No. :<br />

NA<br />

(62) Filed on : NA<br />

(63) Divisional to Application No. :NIL<br />

(64) Filed on : NA<br />

(57) Abstract:<br />

(71) Name <strong>of</strong> the applicant:<br />

International Business Machine Corporation;<br />

Address <strong>of</strong> the Applicant:<br />

Company Organized <strong>and</strong> Existing Under The<br />

Law <strong>of</strong> NEW YORK, United States Of America,<br />

Of Armonk, New York 10504, U.S.A.<br />

(72) Name <strong>of</strong> the Inventor:<br />

BRODSKY William L;<br />

SATHE Sanjeev B.;<br />

THIEL George H.;<br />

A semiconductor chip package having a non–planar chip therein, to reduce the stress<br />

concentrations between the chip <strong>and</strong> cover plate. In particular, a chip <strong>and</strong> method <strong>of</strong> forming a chip<br />

having a non–planar <strong>of</strong> “domed” back surface, wherein the thickness <strong>of</strong> the non–planar chip is<br />

greatest substantially near the center <strong>of</strong> the chip. Further, a method <strong>of</strong> rounding the edges or<br />

corners <strong>of</strong> the chip to reduce crack propagation originating at the edges <strong>of</strong> the chip.<br />

18158

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