24/06/2005 - Controller General of Patents, Designs, and Trade Marks

(21) Application No. 0463/ DEL/1999 A (22) Date of filing of Application: 23/03/1999
(54) Title of the invention: “A PROCESSOR FOR EXECUTING PARTIAL WIDTH PACKED DATA
INSTRUCTIONS.”
(51) International Classification 7 : G06 F9/22,G06 F9/302
(30) Priority Data:
(31) Document No.: 09/053,127
(32) Date: 31/03/1998
(33) Name of convention country: USA
(66) Filed U/s 5(2): NIL
(61) Patent of addition to application No.: NA
(62) Filed on: NA
(63) Divisional to Application No.: NIL
(64) Filed on: NA
Total No Of Page: 40
(57) Abstract:
(71) Name of the applicant:
INTEL CORPORATION
Address of the Applicant:
2200 MISSION COLLEGE
BOULEVARD, SANTA CLARA,
CALIFORNIA 95052, UNITED
STATES OF AMERICA.
(72) Name of the Inventor:
TICKY THAKKAR
PATRICE ROUSSEL
A method and apparatus are provided for executing scalar packed data instructions. According to one
aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to
the plurality of register, a decoder coupled to the register-renaming unit, and a partial-width execution
unit coupled to the decoder. The register renaming unit provides an architectural register file to store
packed data operands each of which include a plurality of data elements. The decoder is configure to
decode a first and second set of instructions that each specify one or more registers in the architectural
register file. Each of the instruction in the first set of instructions specify operations to be performed on
all of the data elements stored in the one or more specified registers. In contrast, each of the
instructions in the second set of instructions specify operations to be performed on only a subset of the
data element stored in the one or more specified registers. The partial-width execution unit is
configured to execute operations specified by either of the first or the second set of instructions.
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