24/06/2005 - Controller General of Patents, Designs, and Trade Marks

(12) PATENT APPLICATION PUBLICATION
(19) INDIA (21)
(22) Date of filing of
Application:
(54) Title of the invention:
25/02/2005 (43)
(51) International
Classification:
G06F 17/50 (71)
(31) Priority Document No.: NIL
(32) Priority Date:
EARLY PUBLICATION
Application No: 211/MUM/2005 A
Publication Date: 24/06/2005
A SYSTEM AND METHOD FOR EMULATING A LOGIC CIRCUIT
DESIGN USING PROGRAMMABLELOGIC DEVICES
NIL
(33) Name of priority country: NIL
(86)
International Application No. & Filing Date:
NIL
NIL
(87) International Publication No.: NIL
(61)
(62)
Patent of addition to Application No.: NIL
Filed on: N.A.
Divisional to
Application No.: NIL
Filed on: N.A.
(72)
Name of the Applicant:
POWAI LABS. TECHNOLOGY PVT.
LTD.
Address of the Applicant:
4 th FLOOR, KRESIT, LLT-BOMBAY,
POWAI, MUMBAI – 400 076, INDIA
Name of the Inventors:
1. MADHAV P. DESAI
2. MITRA SUDHIR PURANDARE
3. HIMANSHU SHARMA
4. SACHIN B. PATKAR
Filed U/S 5(2) before the
Patents (Amendment)
Ordinance, 2004: NO
(57) Abstract : The present system provides a number of hardware and software modules that emulate
logic circuit designs for simulation purposes. The present system receives an intial logic circuit design and
provides algorithms to recode, weight partition and interconnect an emulated logic circuit wherein the
features of the original circuit design are preserved. The system further provides a monitoring of the internal
signals within the emulated circuit.
(FIG. ) : NIL
Total pages : 23
The Patent Office Journal 24.06.2005 17717