24/06/2005 - Controller General of Patents, Designs, and Trade Marks

(21) Application No.00526/DELNP/ 2004 A (22) Date of filing of Application: 03/03/2004
(54) Title of the invention: “MEMORY DEVICE ARCHITECTURE.”
(51) International Classification 7 : G11C
11/408,11/4097,7/18, 8/14
(30) Priority Data:
(31) Document No.: 09/941,053
(32) Date: 28/8/2001
(33) Name of convention country: USA
(66) Filed U/s 5(2): NIL
(61) Patent of addition to application No.: NA
(62) Filed on: NAS
(63) Divisional to Application No.: NIL
(64) Filed on: NA
Total No Of Page: 29
(57) Abstract:
An apparatus, comprising:
(71) Name of the applicant:
INTEL CORPORATION
Address of the Applicant:
State Of Delaware, Of 2200 Mission College
Boulevard, Santa Clara, California 95052, United
States Of America.
(72) Name of the Inventor:
SHIH-LIEN LU
DINESH SOMASEKHAR
VIVEK DE
A row of memory cells comprising a first memory cell and a second memory cell;
A set of word-lines coupled to said row and comprising a word-line to select the first memory cell
independently from the second memory cell; and
Circuitry to sense a difference between a signal on a first bit-line in response to a charge from the
first memory cell and reference on a second bit-line coupled to the second bit-line coupled to the
second memory cell.
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