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24/06/2005 - Controller General of Patents, Designs, and Trade Marks

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(12) PATENT APPLICATION PUBLICATION<br />

(19) INDIA (21) Application No.: IN/PCT/2002/00332/MUM A<br />

(22) Date <strong>of</strong> filing <strong>of</strong> Application: 19/03/2002 (43) Publication Date: <strong>24</strong>/<strong>06</strong>/<strong>2005</strong><br />

(54) Title <strong>of</strong> the invention: : A METHOD OF CONSTRUCTING AN ELECTRONIC ASSEMBLY<br />

(51) International classification : H01L 23/34<br />

(31) Priority Document No : 09/394,860<br />

(32) Priority Date : 13/09/1999<br />

(33) Name <strong>of</strong> priority country : USA<br />

(86) International Application<br />

No <strong>and</strong> Filing Date:<br />

(87) International Publication<br />

No<br />

(61) Patent <strong>of</strong> addition to<br />

Application No<br />

: PCT/US00/23778<br />

29/08/2000<br />

: WO 01/2<strong>06</strong>73 A1<br />

:<br />

NIL<br />

Filed on : N.A.<br />

(62) Divisional to Application<br />

No<br />

: NIL<br />

Filed on : N.A.<br />

(71) Name <strong>of</strong> Applicant:<br />

INTEL CORPORATION<br />

Address <strong>of</strong> the Applicant:<br />

DELAWARE CORPORATION, 2200<br />

MISSION COLLEGE BOULEVARD,<br />

SANTA CLARA, CALIFORNIA 95052,<br />

USA.<br />

(72) Name <strong>of</strong> the Inventor:<br />

1. DISHONGH TERRANCE J.<br />

2. CHURILLA PAUL W.<br />

3. PULLEN DAVID H.<br />

Filed U/S 5(2) before The<br />

<strong>Patents</strong> (Amendment)<br />

Ordinance, 2004: NO<br />

(57) Abstract: According to one aspect <strong>of</strong> the invention a method <strong>of</strong> constructing an electronic assembly is provided. The<br />

electronic assembly is constructed from a semiconductor package including a package substrate <strong>and</strong> a semiconductor chip<br />

mounted to the package substrate, a thermally conductive member, <strong>and</strong> a substance including indium. The method comprises<br />

securing the thermally conductive member <strong>and</strong> the semiconductor pakage in a selected orientation relative to one another<br />

with the thermally conductive member on a side <strong>of</strong> the semiconductor chip opposing the package substrate <strong>and</strong> with the<br />

substance located between the semiconductor chip <strong>and</strong> at least a portion <strong>of</strong> the thermally conductive member. The substance<br />

is thermally coupled to the semiconductor chip on one side <strong>and</strong> thermally coupled to the portion <strong>of</strong> the thermally conductive<br />

member on an opposing side.<br />

Total Pages: 16.<br />

(FIG.- 11.)<br />

The Patent Office Journal <strong>24</strong>.<strong>06</strong>.<strong>2005</strong> 17777

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