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24/06/2005 - Controller General of Patents, Designs, and Trade Marks

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(21) Application No. 319/DEL/2001 A (22) Date <strong>of</strong> filing <strong>of</strong> Application: 21/03/2001<br />

(54) Title <strong>of</strong> the invention: “Stacked Poly–Poly And Mos Capacitor”<br />

(51) International Classification 7 :<br />

H01L 21/8<strong>24</strong>9, H01L 21/20<br />

(30) Priority Data :<br />

(31) Document No.:09/551,168<br />

(32) Date : 17/04/2000<br />

(33) Name <strong>of</strong> convention country :U.S.A.<br />

(66) Filed U/s 5(2) : NIL<br />

(61) Patent <strong>of</strong> addition to application No. :<br />

NA<br />

(62) Filed on : NA<br />

(63) Divisional to Application No. :NIL<br />

(64) Filed on : NA<br />

Total No <strong>of</strong> Pages: 29<br />

(57) Abstract:<br />

(71) Name <strong>of</strong> the applicant:<br />

International Business Machines Corporation,<br />

Address <strong>of</strong> the Applicant:<br />

Armonk, New York, 10504, U.S.A.<br />

(72) Name <strong>of</strong> the Inventor:<br />

COOLBAUGH Douglas D;<br />

DUNN James Stuart;<br />

ST. ONGE Stephen Arthur;<br />

A stacked poly–poly / MOS capacitor useful as a component in a BiCMOS device<br />

comprising a semiconductor substrate having a region <strong>of</strong> a first conductivity–type formed in a<br />

surface there<strong>of</strong>; a gate oxide formed on said semiconductor substrate overlaying said region <strong>of</strong> first<br />

conductivity–type; a first polysilicon layer formed on at least said gate oxide layer, said first<br />

polysilicon layer being doped with an N or P–type dopant; a dielectric layer formed on said first<br />

polysilicon layer; <strong>and</strong> a second polysilicon layer formed on said dielactric layer, said second<br />

polysilicon layer being doped with the same or different dopant as the first polysilicon layer.<br />

18147

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