Développement de modèles pour l'évaluation des performances ...

Bibliographie
[Bidal 09]
G. Bidal, D. Fleury, G. Ghibaudo, F. Boeuf et T. Skotnicki “Guidelines for MOSFET Device
optimization accounting for L-dependent mobility degradation” In Silicon Nano Workshop
2009.
[Boeuf 04] F.Boeuf, F.Amaud, B.Tavel, B. Duriez, M.Bidaud, P. Gouraud, C. Chaton, P. Morin, J.
Todeschini, M. Jurdit, L. Pain, V. De-Jonghe, M.T. Basso, D. Sotta, F. Wacquant, J. Rosa, R.
El-Farhane ,S. Jullian, “A Conventional 45nm CMOS node Low-Cost Platform for General
Purpose and Low Power Applications” IEDM Tech. Dig., pp.425-428, 2004.
[Boeuf 08]
[Boeuf 09]
F. Boeuf, M. Sellier, A. Farcy, and T. Skotnicki « An Evaluation of the CMOS Technology
Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation » in
IEEE Trans. Electron Devices, vol. 55, no6, june 2008, pp 1433-1440.
F. Boeuf, G. Ghibaudo et T.Skotnicki “Impact of Coulomb Scattering on the Characteristics
of Nanoscale Devices” dans International Conference on SSDM 2009.
tel-00820068, version 1 - 3 May 2013
[Boeuf 11]
[BSIM]
F. Boeuf “FDSOI, an innovative technology for low-Vdd / high-performance logic” in a
shortcourse given in ISSCC conference 2011.
BSIM manual, http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4.
[Chan 11] K. Chan, B. Benbakhti, C. Riddet, J. Watling and A. Asenov “Monte Carlo Simulation of a 20
nm Gate Length Implant Free Quantum Well Ge pMOSFET with Different Lateral Spacer
width” in proceedings of ULIS conference 2011.
[Chen 03]
Q. Chen; E.M. Harrell and J.D. Meindl “A physical short-channel threshold voltage model
for undoped symmetric double-gate MOSFETs “ in IEEE Trans. Electron Devices, vol. 50,
no7, jul. 2003, pp 1631-1637.
[Chen 08] X. Chen, S. Samavedam, V. Narayanan, K. Stein, C. Hobbs, C. Baiocco, W. Li, D. Jaeger, M.
Zaleski, H. S. Yang, N. Kim, Y. Lee, D. Zhang, L. Kang, J. Chen H. Zhuang, A. Sheikh, J.
Wallner, M. Aquilino, J. Han, Z. Jin, J. Li, G. Massey, S. Kalpat, R. Jha, N. Moumen, R. Mo, S.
Kirshnan, X. Wang, M. Chudzik, M. Chowdhury, D. Nair, C. Reddy, Y. W. Teh, C.
Kothandaraman, D. Coolbaugh, S. Pandey, D. Tekleab, A. Thean, M. Sherony, C. Lage, J.
Sudijono, R. Lindsay, J. H. Ku, M. Khare, A. Steegen “A Cost Effective 32nm High-K/ Metal
Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process”
in VLSI Symp. Tech. Dig., 2008, pp. 88–89.
[Cheng 11]
K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, B. Haran, A. Kumar, T. Adam, A. Reznicek,
N. Loubet, H. He, J. Kuss, M. Wang, T. M. Levin, F. Monsieur, Q. Liu, R. Sreenivasan, J. Cai,
A. Kimball, S. Mehta, S. Luning, Y. Zhu, Z. Zhu, T. Yamamoto, A. Bryant, C. –H. Lin, S.
Naczas, H. Jagannathan, L. F. Edge, S. Allegret-Maret, A. Dube, S. Kanakasabapathy, S.
Schmitz, A. Inada, S. Seo, M. Raymond, Z. Zhang, A. Yagishita, J. Demarest, J. Li, M.
Hopstaken, N. Berliner, A. Upham, R. Johnson, S. Holmes, T. Standaert, M. Smalley, N.
Zamdmer, Z. Ren, T. Wu, H. Bu,V. Paruchuri, D. Sadana, V. Narayanan, W. Haensch, J.
O'Neill, T. Hook, M. Khare, B. Doris « ETSOI CMOS for System-on-Chip Applications
Featuring 22nm Gate Length, Sub-100nm Gate Pitch, and 0.08μm2 SRAM Cell » in VLSI
Symp. Tech. Dig., 2011, pp. 128–129.
243