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Bibliographie<br />

[ELDO]<br />

[ELDO UDM manual]<br />

[Elmasry 82]<br />

[Ernst 99]<br />

[Ernst 99]<br />

ELDO, www.mentor.com<br />

Eldo UDM/GUDM User’s Manual, www.mentor.com<br />

M. I. Elmasry “Capacitance Evaluation in MOSFET VLSI” IEEE Electron Device Lett., vol.3,<br />

no. 1, jan 82, pp.6-7.<br />

T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, S. Horiguchi, Y. Ono. “Investigation of<br />

SOI MOSFETs with ultimate thickness”, Microelectronics Engineering, Vol.48, pp.339-342,<br />

1999.<br />

T. Ernst and S. Cristoloveanu, “The GP concept for the reduction of short-channel effect in<br />

fully <strong>de</strong>pleted SOI <strong>de</strong>vcies”, SOI Technology and Device IX, Electrochem. Soc., Pennington,<br />

pp.329, 1999.<br />

tel-00820068, version 1 - 3 May 2013<br />

[Ernst 02]<br />

[Ernst 07]<br />

T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu “Fringing fields in sub-0.1 lm fully<br />

<strong>de</strong>pleted SOI MOSFETs: optimization of the <strong>de</strong>vice architecture” Solid State Electronics<br />

Journal 46, pages 373-378, 2002.<br />

T. Ernst, R. Ritzenthaler, O. Faynot et S. Cristoloveanu “A Mo<strong>de</strong>l of Fringing Fields in Short-<br />

Channel Planar and Triple-Gate SOI MOSFETs” IEEE Trans. On Electron Devices, Vol. 54,<br />

n°6, pp.1366-1375 , juin 2007.<br />

[Fenouillet 11] C. Fenouillet-Beranger, P. Perreau, L. Tosti, O. Thomas, J-P. Noel, T. Benoist, O. Weber, F.<br />

Andrieu, A. Bajolet, S. Haendler, M. Cassé, X. Garros, K.K. Bour<strong>de</strong>lle, F. Boedt, O. Faynot, F.<br />

Boeuf “Low power UTBOX and Back Plane (BP) FDSOI technology for 32nm no<strong>de</strong> and<br />

below” in poceedings of ICICDT 2011.<br />

[Fenouillet 12]<br />

C.Fenouillet-Beranger, P. Perreau, O. Weber, I. Ben-Akkez, A. Cros, A. Bajolet, S. Haendler,<br />

P. Fonteneau, P. Gouraud, E. Richard, F. Abbate, D. Barge, D. Pellissier-Tanon, B. Dumont,<br />

F. Andrieu, J. Passieux, R. Bon, V. Barral, D. Golanski, D. Petit, N. Planes, O. Bonin, W.<br />

Schwarzenbach, T. Poiroux, O. Faynot, M. Haond, F. Boeuf “Enhancement of Devices<br />

Performance of hybrid FDSOI/Bulk Technology by using UTBOX sSOI substrates” in VLSI<br />

Tech. Dig., 115-116, 2012.<br />

[Fischetti 01]<br />

[Flandre 10]<br />

[Fleury 09]<br />

[FlexPDE]<br />

M.V. Fischetti, D.A. Neumayer et E.A. Cartier. “Effective electron mobility in Si inversion<br />

layers in metal-oxi<strong>de</strong>-semiconductor systems with a high-k insulator : The role of remote<br />

phonon scattering”. Journal of Applied Physics, vol. 90, no. 9, pages 4587 – 608, 2001.<br />

D. Flandre, V. Kilchytska, and T.Ru<strong>de</strong>nko “gm/Id Method for Threshold Voltage Extraction<br />

Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold” IEEE<br />

Electron Device Lett., Vol. 31, NO. 9, Sept. 2010 pp 930-932.<br />

D. Fleury « Contribution à l’étu<strong>de</strong> expérimentale du transport dans les transistors <strong>de</strong><br />

dimensions déca-nanométriques <strong>de</strong>s technologies CMOS sub-45nm. » Thèse <strong>de</strong> doctorat,<br />

<strong>de</strong> l’institut polytechnique <strong>de</strong> Grenoble, soutenue publiquement en 2009.<br />

www.p<strong>de</strong>solutions.com<br />

245

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