Bibliographie [Chipworks] “Intel’s 22-nm Tri-gate Transistors Exposed” accessible en ligne via http://www.chipworks.com/en/technical-competitive-analysis/resources/technologyblog/2012/04/intel%e2%80%99s-22-nm-tri-gate-transistors-exposed/ [Cho 11] [Choi 11] [Colinge 90] H.-J. Cho, K.-I. Seo, W.C. Jeong, Y.-H. Kim, Y.D. Lim, W.W. Jang, J.G. Hong, S.D. Suk, M. Li, C. Ryou, H.S. Rhee, J.G. Lee, H.S. Kang, Y.S. Son, C.L. Cheng, S.H. Hong, W.S. Yang, S.W. Nam, J.H. Ahn, D.H. Lee, S. Park, M. Sadaaki, D.H. Cha, D.W. Kim, S.P. Sim, S. Hyun, C.G. Koh, B.C. Lee, S.G. Lee, M.C. Kim, Y.K. Bae, B. Yoon, S.B. Kang, J.S. Hong, S. Choi, D.K. Sohn, J. S. Yoon and C. Chung “Bulk Planar 20nm High-K/Metal Gate CMOS Technology Platform for Low Power and High Performance Applications” ”, IEDM Tech. Dig., pp.350,353 2011. H. Choi, J. Lee and W. Sung “Memory Access Pattern-Aware DRAM Performance Mo<strong>de</strong>l for Multi-Core Systems” in ISPASS conference proceedings, pp. 66-75, 2011. J.P. Colinge, M.H. Gao, A. Romano-Rodriguez, H. Maes, C. Claeys, “Silicon-on-insulator gate all around <strong>de</strong>vice”, IEDM Tech. Dig., pp.595, 1990. tel-00820068, version 1 - 3 May 2013 [Coquand 12] R. Coquand, M. Cassé S. Barraud, P. Leroux, D. Cooper, C. Vizioz, C. Comboroure, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, F. Allain, S. Barnola, V. Delaye, F. Aussenac, G. Reimbold, G. Ghibaudo, D. Munteanu, S. Monfray, F. Boeuf, O. Faynot, and T. Poiroux “Strain-Induced Performance Enhancement of Tri-Gate and Omega-Gate Nanowire FETs Scaled Down to 10nm Width” VLSI Tech. Dig., 13-14, 2012. [Dennard 74] [Dewey 12] [Duallogic D4.2] R.H.Dennard, F. H. Gaensslen, H.-N. Yu, V.L. Ri<strong>de</strong>out, E. Bassous et A. R. LeBlanc “Design of ion-implanted mosfet’s with very small physical dimensions.” IEEE Journal of Solid-State Circuits, sc-9(5):256 – 268, 1974. G. Dewey, M. Radosavljevic, and N. Mukherjee “III-V Quantum Well Field Effect Transistors on Silicon for Future High Performance and Low Power Logic Applications” ”, IEDM Tech. Dig., pp.714-718, 2011. “Device simulations of III-V and Ge MOSFETs”, Deliverable D4.2 du projet Duallogic. [Diouf 11] [Dupré 08] [Durand 66] C. Diouf, A. Cros, S. Monfray, J. Mitard, J. Rosa, F. Boeuf et G. Ghibaudo “Transport characterization of Ge pMOSFETs in saturation regime” In proceedings of ESDERC conference 2011. C. Dupré, A. Hubert, S. Becu, M. Jublot, V. Maffini-Alvaro, C. Vizioz, F. Aussenac, C. Arvet, S. Barnola, J.-M. Hartmann, G. Garnier, F. Allain, J.-P. Colonna, M. Rivoire, L. Baud, S. Pauliac, V. Loup, T. Chevolleau, P. Rivallin, B. Guillaumot, G. Ghibaudo, O. Faynot, T. Ernst et S. Deleonibus. “15nm-diameter 3d stacked nanowires with in<strong>de</strong>pen<strong>de</strong>nt gates operation : PhiFET”. In International Electron Devices Meeting. Technical Digest, pages 749 –752, 2008. E. Durand “Electrostatique, Tome 2: problèmes généraux conducteurs” Editions Masson et Cie, 1966. 244
Bibliographie [ELDO] [ELDO UDM manual] [Elmasry 82] [Ernst 99] [Ernst 99] ELDO, www.mentor.com Eldo UDM/GUDM User’s Manual, www.mentor.com M. I. Elmasry “Capacitance Evaluation in MOSFET VLSI” IEEE Electron Device Lett., vol.3, no. 1, jan 82, pp.6-7. T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, S. Horiguchi, Y. Ono. “Investigation of SOI MOSFETs with ultimate thickness”, Microelectronics Engineering, Vol.48, pp.339-342, 1999. T. Ernst and S. Cristoloveanu, “The GP concept for the reduction of short-channel effect in fully <strong>de</strong>pleted SOI <strong>de</strong>vcies”, SOI Technology and Device IX, Electrochem. Soc., Pennington, pp.329, 1999. tel-00820068, version 1 - 3 May 2013 [Ernst 02] [Ernst 07] T. Ernst, C. Tinella, C. Raynaud, S. Cristoloveanu “Fringing fields in sub-0.1 lm fully <strong>de</strong>pleted SOI MOSFETs: optimization of the <strong>de</strong>vice architecture” Solid State Electronics Journal 46, pages 373-378, 2002. T. Ernst, R. Ritzenthaler, O. Faynot et S. Cristoloveanu “A Mo<strong>de</strong>l of Fringing Fields in Short- Channel Planar and Triple-Gate SOI MOSFETs” IEEE Trans. On Electron Devices, Vol. 54, n°6, pp.1366-1375 , juin 2007. [Fenouillet 11] C. Fenouillet-Beranger, P. Perreau, L. Tosti, O. Thomas, J-P. Noel, T. Benoist, O. Weber, F. Andrieu, A. Bajolet, S. Haendler, M. Cassé, X. Garros, K.K. Bour<strong>de</strong>lle, F. Boedt, O. Faynot, F. Boeuf “Low power UTBOX and Back Plane (BP) FDSOI technology for 32nm no<strong>de</strong> and below” in poceedings of ICICDT 2011. [Fenouillet 12] C.Fenouillet-Beranger, P. Perreau, O. Weber, I. Ben-Akkez, A. Cros, A. Bajolet, S. Haendler, P. Fonteneau, P. Gouraud, E. Richard, F. Abbate, D. Barge, D. Pellissier-Tanon, B. Dumont, F. Andrieu, J. Passieux, R. Bon, V. Barral, D. Golanski, D. Petit, N. Planes, O. Bonin, W. Schwarzenbach, T. Poiroux, O. Faynot, M. Haond, F. Boeuf “Enhancement of Devices Performance of hybrid FDSOI/Bulk Technology by using UTBOX sSOI substrates” in VLSI Tech. Dig., 115-116, 2012. [Fischetti 01] [Flandre 10] [Fleury 09] [FlexPDE] M.V. Fischetti, D.A. Neumayer et E.A. Cartier. “Effective electron mobility in Si inversion layers in metal-oxi<strong>de</strong>-semiconductor systems with a high-k insulator : The role of remote phonon scattering”. Journal of Applied Physics, vol. 90, no. 9, pages 4587 – 608, 2001. D. Flandre, V. Kilchytska, and T.Ru<strong>de</strong>nko “gm/Id Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold” IEEE Electron Device Lett., Vol. 31, NO. 9, Sept. 2010 pp 930-932. D. Fleury « Contribution à l’étu<strong>de</strong> expérimentale du transport dans les transistors <strong>de</strong> dimensions déca-nanométriques <strong>de</strong>s technologies CMOS sub-45nm. » Thèse <strong>de</strong> doctorat, <strong>de</strong> l’institut polytechnique <strong>de</strong> Grenoble, soutenue publiquement en 2009. www.p<strong>de</strong>solutions.com 245
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