DIPLOMARBEIT - FG Mikroelektronik, TU Berlin

Technische Universität Berlin
Institut für Mikroelektronik
Lukas Bauer
Current setting:
Synchronous mode: Synthesis Silcsyn
External clock: MClk_in
Rising edge
Period: 1 ns
External reset: RESET_in
Active level high
Asynchronous reset
Resolution scale: ps
Time scale: ns
Language: VHDL-like
Design Variable:
-- constants
constant lo32(32): logic :="00000000000000000000000000000000";
constant hi32(32): logic :="11111111111111111111111111111111";
constant lo31(31): logic :="0000000000000000000000000000000";
constant lo27(27): logic :="000000000000000000000000000";
constant lo16(16): logic :="0000000000000000";
constant hi16(16): logic :="1111111111111111";
constant lo14(14): logic :="00000000000000";
constant hi14(14): logic :="11111111111111";
constant lo8(8): logic :="00000000";
constant hi8(8): logic :="11111111";
constant lo4(4): logic :="0000";
constant hi4(4): logic :="1111";
type int27 is integer(0 to 0x07FFFFFF);
type int16 is integer(0 to 0xFFFF);
type int8 is integer(0 to 0x00FF);
type int5 is integer(0 to 0x001F);
type int4 is integer(0 to 0x000F);
type int3 is integer(0 to 0x0007);
type int2 is integer(0 to 0x0003);
-- pins: name_in
-- name_out
-- name_oe ’1’ for output
-- ’0’ for input
-- pins for host interface
-- AD_in(32): in logic;
AD_out(32): out logic;
AD_oe(32): out logic :=lo32;
-- D_in(32): in logic;
D_out(32): out logic;
D_oe(32): out logic :=lo32;
-- AS_in: in logic;
-- DS_in: in logic;
DS_out: out logic;
DS_oe: out logic :=’0’;
-- BS_in(4): in logic;
CS_in: in logic;
-- RS_in: in logic;
-- HWE_in: in logic;
INT_out: out logic :=’0’;
INT_oe: out logic :=’0’;
Rdy_in: in logic;
-- Rdy_out: out logic;
Rdy_oe: out logic :=’0’;
MUX_in: in logic;
-- pins for memory interface
RCA_out(14): out logic;
RAS_out(4): out logic;
CAS_out(4): out logic;
ACS_out(4): out logic;
MWE_out: out logic;
MOE_out: out logic;
MSF_out: out logic;
MSC_out: out logic;
MD_in(32): in logic;
MD_out(32): out logic;
MD_oe(32): out logic;
-- pins for asynchronous delay control
MSC_del0: out logic;
MSC_del2: out logic;
MSC_del4: out logic;
MSC_del8: out logic;
MTR_del0: out logic;
MTR_del2: out logic;
MTR_del4: out logic;
MTR_del8: out logic;
LD_del0: out logic;
LD_del2: out logic;
LD_del4: out logic;
LD_del8: out logic;
-- pins / other functions
RESET_in: in logic;
MClk_in: in logic;
DWE_out: out logic :=’1’;
-- pins for tests only
R_CONF_out(32): out logic;
R_4_out(32): out logic;
-- PATTN(4): in logic; -- test pattern section
-- (no function)
MBW_ot(2): out logic;
HBW_ot(2): out logic;
PATTN_ot(4): out logic;
ADin_ot(32): out logic;
ASin_ot: out logic;
DSin_ot: out logic;
BSin_ot(4): out logic;
RSin_ot: out logic;
HWEin_ot: out logic;
Rdyout_ot: out logic;
FIFOIN_ot(3): out logic;
FIFOOUT_ot(3): out logic;
CAS_MASK_ot(4): out logic;
ANY_CYCLE_ot: out logic;
MEM_GWRITE_ot: out logic;
GPU_WNUM_ot(4): out logic;
MEM_GREAD_ot: out logic;
GPU_RNUM_ot(4): out logic;
PRE_READ_ot: out logic;
PRE_MASK_ot(32):out logic;
Diplomarbeit
Hochleistungs-Grafikprozessor in Speedchart-VHDL
Abbildung 81: Typen, Konstanten und externe Signale im Design ” TIM“
Anhang D.2
Seite 114